IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 38

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
3.10
or the received data stream can be extracted to the PRBS Generator/
Detector for test in this block. The Receive Payload Control of each
framer operates independently.
3.10.1
05CH) must be set to activate the setting in the indirect registers (from
20H to 7FH of RPLC indirect registers). The following methods can be
executed for test on a per-TS basis:
data of one of the eight framers will be extracted to the PRBS Generator/
Detector when the RXPATGEN (b2, E1-00CH) is ‘0’. The received data
can be extracted in framed or unframed mode, as determined by the
UNF_DET (b0, E1-00CH). In unframed mode, all the 32 time slots are
extracted and the per-timeslot configuration in the TEST (b7, E1-RPLC-
indirect registers - 20~3FH) is ignored. In framed mode, the received
data will only be extracted on the time slot configured by the TEST (b7,
E1-RPLC-indirect registers - 20~3FH). Refer to Chapter 3.12 PRBS
Generator / Detector (PRGD) for details.
the value in the DTRK[7:0] (b7~0, E1-RPLC-indirect registers - 40~5FH)
when the DTRKC/NxTS (b6, E1-RPLC-indirect registers - 20~3FH) of
the corresponding time slot is logic 1. (When it is out of Basic Frame
synchronization, the value in the DTRK[7:0] [b7~0, E1-RPLC-indirect
registers - 40~5FH] will replace the data automatically if the AUTOOOF
[b1, E1-000H] is set. Or, when it is out of Basic Frame synchronization
for 100 ms, the value in the DTRK[7:0] [b7~0, E1-RPLC-indirect regis-
ters - 40~5FH] will replace the data automatically if the AUTORED (b2,
000H) is set. These two kinds of data replacements can be executed
even if the PCCE [b0, E1-05CH] is disabled and they replace all the time
slots.)
the µ-law or A-law milliwatt pattern when the DMW (b4, E1-RPLC-indi-
rect register - 20~3FH) of the corresponding time slot is logic 1. (The mil-
liwatt pattern can be A-law or µ-law, as chosen by the DMWALAW [b3,
E1-RPLC-indirect register - 20~3FH]. Refer to Table 8 & Table 9.)
from the PRBS Generator/Detector will replace the received data of one
of the eight framers when the RXPATGEN (b2, E1-00CH) is ‘1’. The test
pattern can replace the received data in framed or unframed mode, as
determined by the UNF_GEN (b1, E1-00CH). In unframed mode, all 32
time slots are replaced and the per-timeslot configuration in the TEST
(b7, E1-RPLC-indirect registers - 20~3FH) is ignored. In framed mode,
the received data will only replace the time slot configured by the TEST
(b7, E1-RPLC-indirect registers - 20~3FH). Refer to the section of PRBS
GENERATOR / DETECTOR (PRGD) for details.
will be output on the RSDn pin when the SIGNINV and the RINV[1:0]
(b2~0, E1-RPLC-indirect registers - 20~3FH) of the corresponding time
slot are set.
ity.)
Functional Description
Different test patterns can be inserted in the received data stream
To enable the test for the received data stream, the PCCE (b0, E1-
- Selected by the PRGDSEL[2:0] (b7~5, E1-00CH), the received
- Replace the data that will be output on the RSDn/MRSD pin with
- Replace the data that will be output on the RSDn/MRSD pin with
- Selected by the PRGDSEL[2:0] (b7~5, E1-00CH), the test pattern
- Invert the most significant bit, the even bits and/or odd bits that
(The above methods are arranged from highest to lowest in prior-
RECEIVE PAYLOAD CONTROL (RPLC)
E1 MODE
28
the value in the A, B, C, D (b3~0, E1-RPLC-indirect registers - 61~7FH)
when the STRKC (b5, E1-RPLC-indirect registers - 20~3FH) of the cor-
responding time slot allows.
ting in the DTRK[7:0] (b7~0, E1-RPLC-indirect registers - 40~5FH) and
the A, B, C, D (b3~0, E1-RPLC-indirect registers - 61~7FH) respectively
when the RXMTKC (b0, E1-001H) is set. To enable this function, PCCE
(b0, E1-05CH) must be set to ‘1’.
written into the indirect registers is in the D[7:0] (b7~0, E1-05FH). The
read or write operation is determined by the R/WB (b7, E1-05EH). The
indirect registers have a read/write cycle. Before the read/write opera-
tion is completed, the BUSY (b7, E1-05DH) will be set. New operations
on the indirect registers can only be implemented when the BUSY (b7,
E1-05DH) is cleared. The read/write cycle is 490 ns.
Table 8: A-Law Digital Milliwatt Pattern
Table 9: µ-Law Digital Milliwatt Pattern
Bit 0
Bit 0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
- Replace the signaling that will be output on the RSSIGn pin with
The data and signaling of all time slots will be replaced with the set-
Addressed by the A[6:0] (b6~0, E1-05EH), the data read from or
Bit 1
Bit 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 2
Bit 2
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Bit 3
Bit 3
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
Bit 4
Bit 4
T1 / E1 / J1 OCTAL FRAMER
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 5
Bit 5
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
March 5, 2009
Bit 6
Bit 6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 7
Bit 7
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0