IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet
IDT82V2108PX
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Octal Framer IDT82V2108 2975 Stender Way, Santa Clara, Califormia 95054 Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 © 2005 Integrated Device Technology, Inc. Version 4 March 2, 2005 March 5, 2009 Printed ...
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Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos- sible product. IDT does not assume any ...
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FEATURES ........................................................................................................................................................................ 1 APPLICATIONS ................................................................................................................................................................ 1 STANDARDS .................................................................................................................................................................... 1 DESCRIPTION .................................................................................................................................................................. 2 FUNCTIONAL BLOCK DIAGRAM .................................................................................................................................... 3 1 PIN ASSIGNMENT ............................................................................................................................................................ 4 1.1 128 PIN PQFP PACKAGE (TOP VIEW) ........................................................................................................................................................ 4 1.2 144 PIN PBGA PACKAGE (BOTTOM VIEW) ............................................................................................................................................... 5 ...
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IDT82V2108 3.11 RECEIVE SYSTEM INTERFACE (RESI) ..................................................................................................................................................... 30 3.11.1 E1 Mode .......................................................................................................................................................................................... 30 3.11.1.1 Receive Clock Slave Mode .............................................................................................................................................. 30 3.11.1.1.1 Receive Clock Slave RSCK Reference Mode ............................................................................................... 31 3.11.1.1.2 Receive Clock Slave External Signaling Mode .............................................................................................. 33 3.11.1.2 Receive ...
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IDT82V2108 3.15.1.3 Control Over International / National / Extra Bits .............................................................................................................. 80 3.15.1.4 Diagnostics ....................................................................................................................................................................... 80 3.15.1.5 Interrupt Summary ............................................................................................................................................................ 80 3.15.2 T1/J1 Mode ...................................................................................................................................................................................... 81 3.16 HDLC TRANSMITTER (THDLC) .................................................................................................................................................................. 82 3.16.1 E1 Mode .......................................................................................................................................................................................... 82 3.16.2 T1/J1 Mode ...
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IDT82V2108 4.2.4.5 Using TJAT / Timing Option ........................................................................................................................................... 123 5 PROGRAMMING INFORMATION ................................................................................................................................. 124 5.1 REGISTER MAP ......................................................................................................................................................................................... 124 5.1.1 E1 Mode Register Map ................................................................................................................................................................. 124 5.1.2 T1/J1 Mode Register Map ............................................................................................................................................................ 127 5.2 REGISTER DESCRIPTION ........................................................................................................................................................................ 131 5.2.1 E1 ...
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Table 1: Structure of TS0 of CRC Multi-Frame .......................................................................................................................................................... 15 Table 2: Interrupt Sources in the E1 Frame Processor .............................................................................................................................................. 16 Table 3: SF Format .................................................................................................................................................................................................... 18 Table 4: ESF Format .................................................................................................................................................................................................. 18 Table 5: Interrupt Sources in the T1/J1 ...
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IDT82V2108 Table 49: Error Insertion ............................................................................................................................................................................................ 106 Table 50: Default Setting in Receive Path in T1/J1 Mode ......................................................................................................................................... 108 Table 51: Default Setting in Transmit Path in T1/J1 Mode ........................................................................................................................................ 108 Table 52: Various Operation Modes in Receive Path for ...
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Figure 1. 128-Pin PQFP (Top View) ............................................................................................................................................................................. 4 Figure 2. 144-Pin PBGA (Bottom View) ........................................................................................................................................................................ 5 Figure 3. E1 Frame Searching Process ...................................................................................................................................................................... 13 Figure 4. Basic Frame Searching Process .................................................................................................................................................................. 14 Figure 5. HDLC Packet ............................................................................................................................................................................................... 22 Figure 6. ...
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IDT82V2108 Figure 49. Transmit Bit Offset in E1 Mode - 2 ............................................................................................................................................................. 66 Figure 50. Transmit Bit Offset in E1 Mode - 3 ............................................................................................................................................................. 67 Figure 51. Transmit Bit Offset in E1 Mode - 4 ............................................................................................................................................................. 67 Figure 52. Transmit ...
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FEATURES • Octal Framer supporting T1, E1 and J1 formats • Provides programmable system interface to support Zarlink Semi- ® ® conductor Inc. ST-BUS , AT&T CHI and MVIP bus, supporting data rates of 1.544, 2.048 & 8.192 Mb/s; up ...
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IDT82V2108 DESCRIPTION The IDT82V2108 is a flexible feature-rich octal T1/E1/J1 Framer. Controlled by software, the IDT82V2108 can be globally configured as an Octal E1 or T1/J1 Framer. When E1 or T1/J1 has been set globally, the operation mode of each ...
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IDT82V2108 FUNCTIONAL BLOCK DIAGRAM TSCCKA TSCCKB/ MTSCCKB TSCFS/ MTSCFS Transmit System TSFSn/ MTSSIG[1:2] Interface TSSIGn MTSD[1:2] TSDn PRBS Generator /Detector MRSD[1:2] RSDn RSCKn/ MRSSIG[1:2] RSSIGn Receive System MRSFS[1:2] RSFSn Interface RSCCK/ MRSCCK RSCFS/ MRSCFS Functional Block Diagram One of the ...
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IDT82V2108 1 PIN ASSIGNMENT LRD[1] 1 LRCK[1] 2 LRD[2] 3 LRCK[2] 4 LRD[3] 5 LRCK[3] 6 LRD[4] 7 LRCK[4] 8 LTD[1] 9 LTCK[1] 10 LTD[2] 11 LTCK[2] 12 LTD[3] 13 LTCK[3] 14 LTD[4] 15 LTCK[4] 16 BIAS 17 VDDIO[0] 18 ...
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IDT82V2108 1.2 144 PIN PBGA PACKAGE (BOTTOM VIEW TSFS[4]/ A TSD[7] TSD[6] TSSIG[4] RSD[1]/ TSFS[6]/ B TSD[8] MRSD[1] TSSIG[6] RSCK[1]/ RSD[2]/ TSFS[8]/ RSSIG[1]/ C MRSD[2] TSSIG[8] MRSSIG[1] RSCK[2]/ RSFS[2]/ D RSSIG[2]/ VDDIO[3] MRSFS[2] MRSSIG[2] RSCK[3]/ E RSFS[3] ...
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IDT82V2108 2 PIN DESCRIPTION Pin No. Name Type PQFP PBGA LRD[1] Input 1 A2 LRD[ LRD[ LRD[ LRD[ LRD[ LRD[ LRD[ LRCK[1] Input 2 C3 LRCK[2] ...
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IDT82V2108 Pin No. Name Type PQFP PBGA RSFS[1] / MRSFS[1] Output 95 D9 RSFS[2] / MRSFS[2] 90 D11 RSFS[3] 87 E11 RSFS[4] 82 G12 RSFS[5] 79 H12 RSFS[6] 76 J12 RSFS[7] 71 L12 RSFS[8] 68 J10 RSCCK / MRSCCK Input ...
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IDT82V2108 Pin No. Name Type PQFP PBGA TSFS[1] / TSSIG[1] / Output / 114 A7 MTSSIG[1] Input TSFS[2] / TSSIG[2] / 112 B8 MTSSIG[2] TSFS[3] / TSSIG[3] 110 C7 TSFS[4] / TSSIG[4] 106 A10 TSFS[5] / TSSIG[5] 104 D8 TSFS[6] ...
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IDT82V2108 Pin No. Name Type PQFP PBGA LTCK[1] Output 10 C1 LTCK[ LTCK[ LTCK[ LTCK[ LTCK[ LTCK[ LTCK[ XCK Input 117 B6 RST Input 39 M2 ...
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IDT82V2108 Pin No. Name Type PQFP PBGA Input 125 D5 TRST TMS Input 128 B3 TCK Input 126 A3 TDI Input 127 D4 TDO Tri-State 124 C4 BIAS Power 17 G4 VDDIO[0] Power 18 F1 VDDIO[ VDDIO[2] 74 ...
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IDT82V2108 Pin No. Name Type PQFP PBGA GNDC[0] Ground 21 G2 GNDC[ GNDC[2] 86 F10 GNDC[ GNDC[4] 118 A9 GNDC[5:12 TESTSE Input 108 H10 This pin is ...
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IDT82V2108 3 FUNCTIONAL DESCRIPTION 3 MODE SELECTION The IDT82V2108 can be configured as a duplex eight ports E1 framer duplex eight ports T1 framer duplex eight ports J1 1 framer. When ...
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IDT82V2108 search for Basic Fframe alignment patten > 914 CRC search for CRC Multi-Frame errors in alignment pattern if CRCEN = one 1 (refer to CRC Multi-Frame) second Start 8ms and 400ms timer find 2 CRC Multi-Frame alignment patterns within ...
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IDT82V2108 3.2.1.1 Synchronization Searching All the frame synchronization functions can only be executed when the UNF (b6, E1-000H) is ‘0’. 3.2.1.1.1 Basic Frame The algorithm of searching for the E1 Basic Frame alignment pat- tern (as shown in Figure 4) ...
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IDT82V2108 Table 1: Structure of TS0 of CRC Multi-Frame Basic Frame SMF No. / Type 1 (Si bit FAS 1 / NFAS 2 / FAS 3 / NFAS SMF FAS 5 / NFAS 6 / ...
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IDT82V2108 When the above status has lasted for 100 ms, AIS alarm is declared with a logic ‘1’ in the AIS (b2, E1-037H). However, in unframed mode, the detection of AIS alarm is disabled. 3.2.1.2.3 Bit Extraction The Frame Processor ...
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IDT82V2108 Table 2: Interrupt Sources in the E1 Frame Processor No. Sources 7 The out of Basic Frame synchronization condition has lasted for 100 ms. (e.g., the condition in Item No. 4 has lasted for 100 ms.) 8 The calculated ...
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IDT82V2108 3.2.2 T1/J1 MODE In T1/J1 Mode, the Frame Processor searches for the frame align- ment patterns in standard Super-Frame (SF Extended Super- Frame (ESF) framing formats. The format is chosen by the ESF (b4, T1/ J1-020H). The ...
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IDT82V2108 3.2.2.2 Out Of Synchronization Detection & Interrupt A 4-frame capacity buffer is used to store the data when the Frame Processor is searching for SF/ESF synchronization. Once the SF/ESF is synchronized, the buffer is relinquished by the Frame Processor ...
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IDT82V2108 3.3 PERFORMANCE MONITOR (PMON) The Performance Monitor is used to count various performance events in the received data stream within defined intervals. The Perfor- mance Monitor of each framer operates independently. 3.3.1 E1 MODE The PMON block counts the ...
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IDT82V2108 3.4 ALARM DETECTOR (ALMD) - T1/J1 ONLY The Alarm Detector block exists in T1/J1 mode only. It detects the Yellow signal and the AIS (Blue Alarm) signal in SF/ESF in T1/J1 data stream and declares the Yellow alarm, the ...
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IDT82V2108 3.5 HDLC RECEIVER (RHDLC) The HDLC extraction is performed in this block. The HDLC Receiver #1, #2 and # mode or the HDLC Receiver #1 and #2 in T1/J1 ESF mode of each framer operate independently. 3.5.1 ...
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IDT82V2108 RHDLCSEL[1:0] (b7~6, T1/J1-00DH), one of the two HDLC Receiver blocks is accessible to the microprocessor. The HDLC#1 extracts the HDLC link in the DL of the F-bit (its position is shown in Table 4). The HDLC#2 extracts the HDLC ...
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IDT82V2108 3.6 BIT-ORIENTED MESSAGE RECEIVER (RBOM) - T1/J1 ONLY The Bit Oriented Message (BOM) can only be received in the ESF format in T1/J1 mode. The standard of BOM is defined in ANSI T1.403 and in TR-TSY-000194. This block of ...
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IDT82V2108 3.8 ELASTIC STORE BUFFER (ELSB) The Elastic Store Buffer of each framer operates independently. 3.8.1 E1 MODE In Receive Clock Slave mode, a 2-basic-frame depth Elastic Store Buffer is used to synchronize the incoming frames to the Receive Side ...
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IDT82V2108 3.9 RECEIVE CAS/RBS BUFFER (RCRB) The Receive CAS/RBS Buffer of each framer operates indepen- dently. 3.9.1 E1 MODE In the Signaling Multi-Frame synchronization condition, the signal- ing bits are located in TS16, which is Channel Associated Signaling (CAS). Their ...
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IDT82V2108 3.9.2 T1/J1 MODE When the frame is synchronized, the signaling is located in the Bit 8 of Frame 6 (A bit) and Frame 12 (B bit format, and is located in the Bit 8 of Frame 6 ...
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IDT82V2108 3.10 RECEIVE PAYLOAD CONTROL (RPLC) Different test patterns can be inserted in the received data stream or the received data stream can be extracted to the PRBS Generator/ Detector for test in this block. The Receive Payload Control of ...
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IDT82V2108 3.10.2 T1/J1 MODE To enable the test for the received data stream, the PCCE (b0, T1/ J1-050H) must be set to activate the setting in the indirect registers (from 01H to 48H). The following methods can be used for ...
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IDT82V2108 3.11 RECEIVE SYSTEM INTERFACE (RESI) The Receive System Interface determines how to output the received data to the system back-plane. The data from the eight framers can be aligned with each other or be output independently. The timing clocks ...
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IDT82V2108 the data streams for all eight framers. RSCFS asserts on each Basic Frame and its valid polarity is configured by the FPINV (b6, E1-011H). The framing signals on RSCFS can also be ignored by setting the FPMODE (b5, E1-011H) ...
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IDT82V2108 The DE (b4, E1-010H) is logic 0 and the FE (b3, E1-010H) is logic 0. The timeslot offset and the bit offset enable are both 0: RSCFS RSCCK RSFSn RSDn TS31 (The RSCKn is selected ...
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IDT82V2108 3.11.1.1.2 Receive Clock Slave External Signaling Mode In this mode (refer to Figure 12), the data on the system interface is clocked by RSCCK. The active edge of RSCCK used to sample the RSCCK RSCFS * RSD[1:8] * Receive ...
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IDT82V2108 The CMS (b2, E1-010H) is logic 0, i.e., the bankplane rate is 2.048Mbit/s. The DE (b4, E1-010H) is logic 1 and the FE (b3, E1-010H) is logic 0. The timeslot offset and the bit offset enable are both 0: ...
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IDT82V2108 3.11.1.2 Receive Clock Master Mode In the Receive Clock Master mode, each framer uses its own clock signal on the RSCKn pin and framing signal on the RSFSn pin to output the data on each RSDn pin. As the ...
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IDT82V2108 RSCK is 2.048M: RSCKn When the DE (b4, E1-010H) is logic 0 and the FE (b3, E1-010H) is logic 0: RSFSn RSDn When the DE (b4, E1-010H) is logic 1 and the FE (b3, E1-010H) is ...
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IDT82V2108 3.11.1.2.2 Receive Clock Master Fractional E1 (with F-bit) Mode Besides all the common functions described in the Receive Clock Master mode, the special feature in this mode (refer to Figure 17) is that RSD[1:8] * RSFS[1:8] * RSCK[1:8] Note: ...
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IDT82V2108 RSCK is 2.048M. In this example, RSCK is supposed to be held in an inactive state during TS0. When the DE (b4, E1-010H) is logic 0 and the FE (b3, E1-010H) is logic 0: RSCKn RSFSn RSDn 1 2 ...
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IDT82V2108 3.11.1.3 Receive Multiplexed Mode In this mode (refer to Figure 19), two multiplexed buses are used to receive data from all eight framers. The data from up to four framers is byte-interleaved and output on one of the two ...
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IDT82V2108 When it is for framing pulse indication, the valid polarity of MRSFS is configured by the FPINV (b6, E1-011H). The FPINV (b6, E1-011H) of the eight framers should be set to the same value. In the Receive Multiplexed mode, ...
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IDT82V2108 3.11.1.4 Parity Check & Polarity Fix In all the above modes except for the Receive Clock Slave Frac- tional E1 (with F-bit) mode, if the RPTYE (b6, E1-012H) is logic 1, parity check will be conducted over the bits ...
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IDT82V2108 For example: when DE (b4, E1-010H (b3, E1-010H RSCFS RSCCK The bit offset is 0: RSDn TS31 The bit offset is set as: BOFF_EN (b3, E1-014H BOFF[2:0] (b2~0, ...
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IDT82V2108 Table 19: Bit Offset Between RSFSn and RSDn When the BRXSMFP and the ALTIFP (b2, b0, E1-011H) are Both Set To Logical 1 BOFF_EN (b3, E1-014H) FPMODE (b5, E1-011H 3.11.1.6 Output On RSDn/MRSD & RSSIGn/MRSSIG In all ...
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IDT82V2108 3.11.2 T1/J1 MODE In T1/J1 mode, the Receive System Interface can be set in Non- multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the RSDn pin is used to output the received data from each framer at a ...
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IDT82V2108 3.11.2.1 Receive Clock Slave Mode In the Receive Clock Slave Mode, the bit rate on the RSDn pin is 1.544Mb/s. However, if the system clock rate is 2.048MHz, the received data stream (1.544 Mb/s) should be converted to the ...
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IDT82V2108 The RSCFSFALL (b1, T1/J1-003H) is logic 0 and the RSCCKRISE (b0, T1/J1-003H) is logic 0. RSCFS RSCCK RSFSn RSDn (The RSCKn is selected by the RSCKSEL (b5, T1/J1-001H) to output a jitter attenuated 1.544MHz (i.e., ...
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IDT82V2108 The CMS (b4, T1/J1-078H) is logic 1, i.e., the bankplane clock rate is 4.096Mbit/s. The RSCFSFALL (b1, T1/J1-003H) is logic 0 and the RSCCKRISE (b0, T1/J1-003H) is logic 1. RSCFS RSCCK RSFSn RSDn (The RSCKn ...
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IDT82V2108 The CMS (b4, T1/J1-078H) is logic 0 and the bankplane clock rate is 1.544Mbit/s. The RSCFSFALL (b1, T1/J1-003H) is logic 1 and the RSCCKRISE (b0, T1/J1-003H) is logic 0. RSCFS RSCCK RSFSn RSDn RSSIGn X ...
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IDT82V2108 The CMS (b4, T1/J1-078H) is logic 1, i.e., the bankplane clock rate is 4.096Mbit/s. The RSCFSFALL (b1, T1/J1-003H) is logic 1 and the RSCCKRISE (b0, T1/J1-003H) is logic 1. RSCFS RSCCK When the RSD_RSCFS_EDGE (b5, T1/J1-078H) is logic 1: ...
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IDT82V2108 3.11.2.2 Receive Clock Master Mode In the Receive Clock Master mode, each framer uses its own clock signal on the RSCKn pin and framing signal on the RSFSn pin to output the data on each RSDn pin. In the ...
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IDT82V2108 3.11.2.2.2 Receive Clock Master Fractional T1/J1 Mode Besides all the common functions described in the Receive Clock Master mode, the special feature in this mode (refer to Figure 17) is that RSCKn is a gapped 1.544MHz clock (no clock ...
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IDT82V2108 3.11.2.3 Receive Multiplexed Mode In this mode (refer to Figure 19), two multiplexed buses are used to receive the data from all eight framers. The data from up to four framers is byte-interleaved output on one of the two ...
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IDT82V2108 The TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001, the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011, the BOFF_EN of the four Framers are ...
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IDT82V2108 For example: when RSCFSFALL (b1, T1/J1-003H RSCCKRISE (b0, T1/J1-003H RSCFS RSCCK The bit offset is 0: RSDn CH24 The bit offset is set as: BOFF_EN (b3, T1/J1-078H BOFF[2:0] (b2~0, ...
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IDT82V2108 3.12 PRBS GENERATOR / DETECTOR (PRGD) The PRBS Generator/Detector is shared by eight framers. It can be assigned to any of the 8 framers at one time. The PRGD, together with the Receive / Transmit Payload Control blocks, is ...
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IDT82V2108 3 kinds of interrupts can be generated by this block: - bit errors; - synchronization status change (indicated in the SYNCI [b3, E1- 071H]); - the PD[31:0] (b7~0, E1-07CH & b7~0, E1-07DH & b7~0, E1- 07EH & b7~0, E1-07FH) ...
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IDT82V2108 3.13 TRANSMIT SYSTEM INTERFACE (TRSI) The Transmit System Interface determines how to input the data to the chip. The input data to the eight framers can be aligned with each other or inputted independently. The timing clocks and framing ...
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IDT82V2108 3.13.1.1.1 Transmit Clock Slave TSFS Enable Mode In this mode (refer to Figure 37), the data on the system interface is clocked by TSCCKB. The active edge of TSCCKB used to sample the TSCCKA TSCCKB TSCFS * TSD[1:8] * ...
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IDT82V2108 The CMS (b2, E1-018H) is logic 0, i.e., the backplane clock rate is 2.048Mbit/s. TSCCKB TSCFS TSDn (When the TSFSRISE (b2, E1-002) is logic 0:) TSFSn (When the TSFSRISE (b2, E1-002) is logic 1:) TSFSn Figure ...
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IDT82V2108 3.13.1.1.2 Transmit Clock Slave External Signaling Mode In this mode (refer to Figure 40), the data on the system interface is clocked by TSCCKB. The active edge of TSCCKB used to sample the TSCCKA TSCCKB TSCFS * TSD[1:8] * ...
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IDT82V2108 The CMS (b2, E1-018H) is logic 1, i.e., the bankplane clock rate is 4.096Mbit/s. TSCCKB TSCFS TSDn TSSIGn Figure 42. E1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 2 3.13.1.2 ...
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IDT82V2108 LTCK is 2.048M LTCKn When the TSFSRISE (b2, E1-002H) is logic 0 and the DE (b4, E1-018H) is logic 1: TSFSn TSDn When the TSFSRISE (b2, E1-002H) is logic 1 and the DE (b4, E1-018H) is ...
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IDT82V2108 3.13.1.3 Transmit Multiplexed Mode In this mode (refer to Figure 45), two multiplexed buses are used to input the data to all eight framers. Chosen by the MTBS (b4, E1-003H) in each framer, the data on one of the ...
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IDT82V2108 MTSCFS MTSCCKB MTSD Framer1_TS31 MTSSIG Line Interface (of any of the Framer1 to Framer4): LTCK n TS31-8 LTDn TS31-7 Figure ...
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IDT82V2108 3.13.1.4 Parity Check In all the above four modes, parity check is calculated over the bits in the previous Basic Frame and the result is inserted into the first bit (MSB) of TS0 on the TSDn/MTSD pin. The even ...
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IDT82V2108 For example: in Transmit Clock Slave mode, CMS (b2, E1-018H (b3, E1-018H (b4, E1-018H TSCFS TSCCKB The CHI (b3, E1-01CH and the bit offset is 0: TSDn 1 2 ...
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IDT82V2108 For example: in Transmit Clock Slave mode, CMS (b2, E1-018H (b4, E1-018H (b3, E1-018H TSCFS TSCCKB The CHI (b3, E1-01CH and the bit offset is 0: TSDn 2 3 ...
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IDT82V2108 For example: in Transmit Clock Master mode, DE (b4, E1-018H TSFSRISE (b2, E1-002H TSFSn LTCKn The bit offset is 0: TSDn 2 1 The bit offset is set as: BOFF[2:0] (b2~0, E1-01CH) = 001; i.e. ...
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IDT82V2108 3.13.2 T1/J1 MODE In T1/J1 mode, the Transmit System Interface can be set in Non- multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the TSDn pin is used to input the data to each framer at a bit ...
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IDT82V2108 3.13.2.1 Transmit Clock Slave Mode In the Transmit Clock Slave mode, the bit rate on the TSDn pin is 1.544 Mb/s. However, if the system clock rate is 2.048MHz, the data to be transmitted should be converted into the ...
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IDT82V2108 The CMS (b5, T1/J1-015H) is logic 0. The bankplane rate is 1.544Mbit/s. TSCCKB TSCFS TSDn (When the TSFSRISE (b5, T1/J1-004) is logic 0:) TSFSn (When the TSFSRISE (b5, T1/J1-004) is logic 1:) TSFSn Figure 54. T1/J1 ...
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IDT82V2108 The TSCCKBFALL (b3, T1/J1-004H) is logic 0. The COFF (b4, T1/J1-015H its default value. TSCCKB TSCFS TSDn (When the TSFSRISE (b5, T1/J1-004) is logic 0:) TSFSn (When the TSFSRISE (b5, T1/J1-004) is logic 1:) ...
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IDT82V2108 The CMS (b5, T1/J1-015H) is logic 0. The bankplane rate is 2.048Mbit/s. TSCCKB TSCFS TSDn TSSIGn Figure 58. T1/J1 Transmit Clock Slave External Signaling Mode - Functional Timing Example 2 TSCCKB TSCFS TSDn ...
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IDT82V2108 3.13.2.2 Transmit Clock Master Mode In the Transmit Clock Master mode (refer to Figure 43), the Trans- mit Side System Common Clock A (TSCCKA) and Transmit Side Sys- tem Common Clock B (TSCCKB) provided by the system side are ...
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IDT82V2108 3.13.2.3 Transmit Multiplexed Mode In this mode (refer to Figure 45), two multiplexed buses are used to input the data to all eight framers. Chosen by the MTBS (b6, T1/J1- 015H) in each framer, the data on one of ...
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IDT82V2108 MTSCFS MTSCCKB MTSD X X Parity Parity F-bit Framer1 bit bit MTSSIG Line Interface (of any of the Framer1 to Framer4). ...
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IDT82V2108 For example: in Transmit Clock Slave mode, CMS (b5, T1/J1-015H TSCCKBFALL (b3, T1/J1-004H TSCFS TSCCKB The bit offset is 0: TSDn The bit offset is set as: BOFF[2:0] (b2~0, E1-01CH) = 010; ...
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IDT82V2108 3.14 TRANSMIT PAYLOAD CONTROL (TPLC) Different test patterns can be inserted in the data to be transmitted or the data to be transmitted can be extracted to the PRBS Generator/ Detector for test in this block. The Transmit Payload ...
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IDT82V2108 - Replace the signaling input from the TSSIGn pin with the value in the (b3~0, T1/J1-TPLC-indirect registers - 31~48H) when the SIGC[1:0] (b7~6, T1/J1-TPLC-indirect registers - 31~48H) is configured. The data of all channels can ...
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IDT82V2108 Table 36: Remote Alarm Indication REMAIS(b3, E1-041H) AUTOYELLOW(b3, E1-000H) G706RAI(b0, E1-00EH When CRC-4 Multi-Frame is generated, the International bits of Frame 13 & 15 (E1 & E2 bits) are used for FEBE indication ...
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IDT82V2108 Table 38: Interrupt Summary in E1 Mode No. 1 The end of the first frame of a Signaling Multi-Frame is input to the Frame Generator when Signaling Multi- Frame is generated and coincides with the CRC Multi-Frame. 2 The ...
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IDT82V2108 3.16 HDLC TRANSMITTER (THDLC) The HDLC data insertion is performed in this block. The HDLC Transmitters #1, #2 and # mode or the HDLC Transmitter #1 and #2 in T1/J1 mode ESF format of each framer operate ...
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IDT82V2108 the current entire HDLC frame is indicated by the EOM (b3, T1/J1- 034H). When it is set, the HDLC data should be transmitted even if it does not exceed the upper threshold of the FIFO. The FCS, if enabled ...
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IDT82V2108 3.19 JITTER ATTENUATOR (RJAT/TJAT) The Jitter Attenuator of each framer operates independently 3.19.1 E1 MODE Two Jitter Attenuators are provided independently in the receive path and the transmit path. The Jitter Attenuator integrates a FIFO and a DPLL. The ...
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IDT82V2108 Amp.(UI) 100 10 4.88x10 -3, 36.9UI 1 0.1 0.001 0.01 Attenuation(db) 0 9Hz,-3db 1 10 Functional Description 7Hz,64UI 9Hz,43UI 1.667,18UI 18UI G.823 20,1.5UI 0 100 Figure 65. E1 Mode Jitter Tolerance ( 2fH) 40Hz,0.5db ...
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IDT82V2108 3.19.2 T1/J1 MODE Two Jitter Attenuators are provided independently in the receive path and the transmit path. The Jitter Attenuator integrates a FIFO and a DPLL. The smoothed clock output from the jitter attenuator is generated by adaptively dividing ...
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IDT82V2108 UI(jitter) Amp.(UI) 100 138UI 4.9Hz,28UI 10 0.31Hz,10UI 1 TR-TSY-000170 0.1 0.1 1 Figure 67. T1/J1 Mode Jitter Tolerance ( 2fH) Attenuation(Db) 0 -20 -40 -60 -80 1 Functional Description 4Hz,76UI 12Hz,45UI 300Hz,10UI 10Hz,0.3UI 10 100 20Hz,0db ...
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IDT82V2108 3.20 TRANSMIT CLOCK The Transmit Clock of each framer operates independently. 3.20.1 E1 MODE The Transmit Clock helps the Transmit Jitter Attenuator to select the source of the input reference clock for the DPLL, and selects the clock source ...
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IDT82V2108 3.21 LINE INTERFACE 3.21.1 E1 MODE On the receive line interface, the received data on the LRDn pin is sampled on the active edge of LRCKn. The active edge of LRCKn is chosen by the RCKFALL (b7, E1-001H). On ...
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IDT82V2108 3.23 LOOPBACK MODE There are three diagnostic loopback modes: Line Loopback, Digital Loopback and Payload Loopback are provided in this device. 3.23.1 LINE LOOPBACK By programming the LINEB (b4, E1-007H / b4, T1/J1-00AH), each framer can be set in ...
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IDT82V2108 3.23.2 DIGITAL LOOPBACK By programming the DDLB (b2, E1-007H / b2, T1/J1-00AH), each framer can be set in the Digital Loopback mode. In this configuration, the data to be transmitted on LTCKn and LTDn is looped internally to the ...
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IDT82V2108 3.23.3 PAYLOAD LOOPBACK By programming the LOOP (b2, E1-TPLC-indirect registers- 20~3FH / b2, T1/J1-TPLC-indirect registers-10~18H) (the PCCE [b0, E1-060H / b0, T1/J1-030H] in the TPLC must be logic 1), each framer can be set in the Payload Loopback mode. ...
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IDT82V2108 3.24 CLOCK MONITOR The transition from low to high of the Crystal Clock (XCK), the Transmit Side System Common Clock #A (TSCCKA), the Transmit Side System Common Clock #B (TSCCKB), the Receive Side System Com- mon Clock (RSCCK) and ...
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IDT82V2108 4 OPERATION 4.1 E1 MODE 4.1.1 DEFAULT SETTING When the device is powered-up, all the registers contain their default values. Any of the eight framers can be reset anytime when the RESET (b0, E1-00AH / b0, T1/J1-00DH) in its ...
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IDT82V2108 4.1.2 VARIOUS OPERATION MODES CONFIGURATION Five operation modes can be set in the receive path and four oper- ation modes can be set in the transmit path. In each operation mode, the configurations in Table 41 and Table 42 ...
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IDT82V2108 Table 41: Various Operation Modes in Receive Path for Reference (Continued) 1 Mode Value (from Bit7 to Bit0) Register 011H 091H 111H 191H 211H 291H 311H 391H 012H 092H 112H Receive Multi- 192H plexed Mode 212H (Continued) 292H 312H ...
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IDT82V2108 Table 42: Various Operation Modes in Transmit Path for Reference (Continued) 1 Mode Value (from Bit7 to Bit0) Register 018H Transmit Clock 040H Master Mode 004H 003H 083H 103H 183H 203H 283H 303H 383H 018H 098H 118H 198H 218H ...
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IDT82V2108 Table 42: Various Operation Modes in Transmit Path for Reference (Continued) 1 Mode Value (from Bit7 to Bit0) Register 027H 0A7H 127H Transmit Multi- 1A7H plexed Mode 227H (Continued) 2A7H 327H 3A7H Note the ‘Register’ column, except ...
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IDT82V2108 store the packet data Discard this data byte, Set LINK ACTIVE * Flag Note: * The PACKET COUNT, EMPTY FIFO and LINK ACTIVE are local software variable. Figure 73. Interrupt Service in E1 Mode HDLC Receiver Operation INT asserts ...
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IDT82V2108 To summarize the procedure of using HDLC Receive, a complete example is shown in Table 43. Table 43: Example for Using HDLC Receiver Register Value 00AH 50H RHDLC #2 is selected. The HDLC Receive is accessible to the CPU ...
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IDT82V2108 Set the RLP Flag Note: 1. RLP-Retransmit the last packet, a local software variable local timer to wait for a certain time until the Full = 0 or the BLFILL = 1. Figure 75. Interrupt Service in ...
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IDT82V2108 - Polling Mode In the packet transmission polling mode, the FULLE (b3, E1-053H), OVRE (b2, E1-053H), UDRE (b1, E1-053H) and LFILLE (b0, E1-053H) should be set to logic 0. The THDLC Lower Transmit Threshold should be set to such ...
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IDT82V2108 4.1.3.3 Using PRBS Generator / Detector The IDT82V2108 provides one PRBS generator/detector block to generate and detect an enormous variety of pseudo-random and repeti- Table 45: Test Pattern in E1 Mode Pattern Type ...
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IDT82V2108 The PRBS generator/detector block can be used to test E1 line transmit-receive integrity and system backplane integrity. - Example For Testing E1 Line Transmit-Receive Integrity To monitor the errors in Framer 2 without taking the entire E1 span off ...
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IDT82V2108 Table 47: Initialization of TPLC (Continued) Register 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H 0E3H 0E2H ...
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IDT82V2108 Table 48: Initialization of RPLC (Continued) Register 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH 0DFH 0DEH ...
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IDT82V2108 4.1.3.4 Using Payload Control and Receive CAS/RBS Buffer Before using the Receive/Transmit Payload Control and Receive CAS/RBS Buffer, the indirect registers of these blocks must be initialized to eliminate erroneous control data. The PCCE (b0, E1-05CH & b0, E1- ...
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IDT82V2108 - Transmit Multiplexed Mode (System Backplane Rate: 8.192 Mbit/s) TSCCKA is selected as the TJAT DPLL input reference clock. TSC- CKA is equal to 2.048 M. The N1 (b7~0, E1-025H) and N2 (b7~0, E1- 026H) are set to their ...
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IDT82V2108 4.2.2 OPERATION IN J1 MODE The IDT82V2108 can also be operated in J1 mode when the TEMODE (b0, 400H) is set to logic 1. Except for the setting of the JYEL in bit 3 of FRMP Configuration registers (020H, ...
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IDT82V2108 Table 52: Various Operation Modes in Receive Path for Reference (Continued) 1 Mode Value (from Bit7 to Bit0) Register 001H 003H 020H Receive Clock Master Frac- tional T1/J1 02CH Mode 040H 050H 01H-18H (RPLC Indirect Registers) 001H 081H 101H ...
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IDT82V2108 Table 52: Various Operation Modes in Receive Path for Reference (Continued) 1 Mode Value (from Bit7 to Bit0) Register 02CH 0ACH 12CH 1ACH 22CH 2ACH 32CH Receive Multi- 3ACH plexed Mode 040H (Continued) 0C0H 140H 1C0H 240H 2C0H 340H ...
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IDT82V2108 Table 53: Various Operation Modes in Transmit Path for Reference (Continued) 1 Mode Value (from Bit7 to Bit0) Register 004H 00000110 Transmit Clock 005H 01000000 Master Mode 044H 00000000 007H 00100100 004H 00001000 084H 00001000 104H 00001000 184H 00001000 ...
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IDT82V2108 Table 53: Various Operation Modes in Transmit Path for Reference (Continued) 1 Mode Value (from Bit7 to Bit0) Register 007H 00011101 087H 00011101 107H 00011101 187H 00011101 207H 00011101 287H 00011101 307H 00011101 387H 00011101 019H 099H 119H 199H ...
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IDT82V2108 4.2.4 OPERATION EXAMPLE In this chapter, some common operation examples are given for reference. 4.2.4.1 Using HDLC Receiver In T1/J1 mode, the HDLC Receive can only be used in the ESF for- mat. Before using the HDLC#2 Receive, the ...
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IDT82V2108 store the packet data Discard this data byte, Set LINK ACTIVE * Flag Note: * The PACKET COUNT ,EMPTY FIFO and LINK ACTIVE is a local software variable Figure 79. Interrupt Service in T1/J1 Mode HDLC Receiver Operation INT ...
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IDT82V2108 To summarize the procedure of using HDLC Receive, a complete example is shown in Table 54. Table 54: Example for Using HDLC Receiver Register Value 00DH 50H RHDLC #2 is selected. The HDLC Receive is accessi- ble to the ...
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IDT82V2108 Set the RLP Flag Note: 1. RLP-Retransmit the last packet, a local software variable local timer to wait for a certain time until the Full = 0 or the BLFILL = 1. Figure 81. Interrupt Service in ...
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IDT82V2108 - Polling Mode In packet transmission polling mode, the FULLE (b3, T1/J1-037H), OVRE (b2, T1/J1-037H), UDRE (b1, T1/J1-037H) and LFILLE (b0, T1/ J1-037H) should be set to logic 0. The THDLC Lower Transmit Thresh- Figure 82. Polling Mode in ...
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IDT82V2108 4.2.4.3 Using PRBS Generator / Detector The IDT82V2108 provides one PRBS generator/detector block to generate and detect an enormous variety of pseudo-random and repeti- Table 56: Test Pattern in T1/J1 Mode Pattern Type ...
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IDT82V2108 The PRBS generator/detector block can be used to test T1/J1 line transmit-receive integrity and system backplane integrity. - Example For Testing T1/J1 Line Transmit-Receive Integrity Suppose to monitor the errors in Framer 2 without taking the entire T1/J1 offline. ...
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IDT82V2108 Table 58: Initialization of TPLC (Continued) Register 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H 0B3H 0B2H ...
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IDT82V2108 Table 59: Initialization of RPLC (Continued) Register 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H 0D3H 0D2H Then set the TEST in RPLC Payload Control register for CH2, CH4 and CH5. The process is: Register Value 0D3H 08H Set the TEST ...
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IDT82V2108 Set PCCE=1 BUSY=0 RWB=1 and address is specified in the Channel Indirect Address/ Control Register. BUSY=0 Read Channel Indirect Data Buffer Register Y More data to be read End Figure 84. Reading Sequence of Indirect Register in T1/ J1 ...
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IDT82V2108 5 PROGRAMMING INFORMATION The Micro-Processor Interface provides the logic to connect the microprocessor interface. For all accesses, CS must be low. The data bus and address bus of the interface can work in the multiplexed on non-multiplexed mode. In ...
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IDT82V2108 Table 62: E1 Mode Register Map - Direct Register (Continued) Framer 1 Framer 2 Framer 3 Framer4 020 0A0 120 1A0 021 0A1 121 1A1 022 0A2 122 1A2 023 0A3 123 1A3 024 0A4 124 1A4 025 0A5 ...
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IDT82V2108 Table 62: E1 Mode Register Map - Direct Register (Continued) Framer 1 Framer 2 Framer 3 Framer4 049 0C9 149 1C9 04A 0CA 14A 1CA 04B 0CB 14B 1CB 04C 0CC 14C 1CC 04D 0CD 14D 1CD 04E ~ ...
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IDT82V2108 Table 62: E1 Mode Register Map - Direct Register (Continued) Framer 1 Framer 2 Framer 3 Framer4 Table 63: E1 Mode Register Map - Indirect Register RPLC Indirect Registers TPLC Indirect Registers RCRB Indirect Registers 5.1.2 T1/J1 MODE REGISTER ...
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IDT82V2108 Table 64: T1/J1 Mode Register Map - Direct Register (Continued) Framer 1 Framer 2 Framer 3 011 091 111 012 092 112 013 093 113 014 094 114 015 095 115 016 ~ 017 096 ~ 097 116 ~ ...
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IDT82V2108 Table 64: T1/J1 Mode Register Map - Direct Register (Continued) Framer 1 Framer 2 Framer 3 042 0C2 142 043 0C3 143 044 0C4 144 045 0C5 145 046 0C6 146 047 0C7 147 048 0C8 148 049 0C9 ...
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IDT82V2108 Table 64: T1/J1 Mode Register Map - Direct Register (Continued) Framer 1 Framer 2 Framer 3 071 0F1 171 072 ~ 076 0F2 ~ 0F6 172 ~ 176 077 0F7 177 078 0F8 178 Table 65: T1/J1 Mode Register ...
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IDT82V2108 5.2 REGISTER DESCRIPTION Mode Selection (400H) Bit No Bit Name Type Default TEMODE: This bit chooses the operation mode globally for the chip The chip operates in the E1 mode. ...
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IDT82V2108 5.2.1 E1 MODE E1 Receive Path Line Options (000H, 080H, 100H, 180H, 200H, 280H, 300H, 380H) Bit No Bit Name FIFOBYP UNF Type R/W R/W Default 0 0 FIFOBYP: This bit decides whether the received data should ...
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IDT82V2108 AUTOUPDATE: This bit decides whether the PMON and PRGD registers are automatically updated once every second The PMON and PRGD registers are not automatically updated. They can only be updated by MCU operation The PMON ...
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IDT82V2108 isters on per time slot basis. This bit only has effect in the Receive Clock Slave mode, and it affects the corresponding time slot of multiplexed bus MRSD when multiplexed bus operation is enabled ELSB Idle Code ...
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IDT82V2108 E1 Transmit Side System Interface Options (003H, 083H, 103H, 183H, 203H, 283H, 303H, 383H) Bit No Bit Name TSSIG_EN Type Reserved R/W Default 1 TSSIG_EN: In Transmit Clock Slave mode (TSCKSLV = 1, b5, E1-018H), this bit ...
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IDT82V2108 E1 Interrupt Source #1 (005H, 085H, 105H, 185H, 205H, 285H, 305H, 385H) Bit No Bit Name PMON FRMG Type R R Default X X Bits in this register indicate which function block introduced an interrupt signal on ...
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IDT82V2108 E1 Diagnostics (007H, 087H, 107H, 187H, 207H, 287H, 307H, 387H) Bit No Bit Name Type Reserved Default LINELB: Line Loopback means that the transmit line interface data and clock (LTDn and LTCKn) are internal directly comes from ...
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IDT82V2108 E1 Revision / Chip ID / Global PMON Update (009H) Bit No Bit Name TYPE[2] TYPE[1] Type R R Default 0 0 Writing to this register causes all Performance Monitor and PRGD Generator/Detector counters to be updated ...
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IDT82V2108 E1 Data Link Micro Select / Framer Reset (00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH) Bit No Bit Name RHDLCSEL[1] RHDLCSEL[0] Type R/W R/W Default X X RHDLCSEL[1:0]: The RHDLCSEL[1:0] select one of the three HDLC ...
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IDT82V2108 E1 Interrupt ID (00BH) Bit No Bit Name INT[8] INT[7] Type R R Default X X This register indicates which one of the eight framers introduced the interrupt INT pin to be logic low. When any one ...
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IDT82V2108 E1 Clock Monitor (00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH) Bit No Bit Name Type Reserved Default This register provides activity monitoring on the IDT82V2108 clocks. When a monitored clock signal makes a low to high ...
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IDT82V2108 E1 Receive Path Frame Pulse Configuration (00EH, 08EH, 10EH, 18EH, 20EH, 28EH, 30EH, 38EH) Bit No Bit Name Type Default PERTS_RSFS, REF_MRSFS: PERTS_RSFS REF_MRSFS 0 0 The pulse output on the RSFS/MRSFS pin is forced to be ...
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IDT82V2108 ‘Full E1’ mode means that the received entire frame (256 bits) is clocked out from the RSDn pin, and there are no gaps in the RSCKn clock pulse. ‘Fractional E1’ mode means that RSCKn only clocks out on the ...
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IDT82V2108 E1 Receive Backplane Frame Pulse Configuration (011H, 091H, 111H, 191H, 211H, 291H, 311H, 391H) Bit No Bit Name FPINV Type Reserved R/W Default 0 FPINV Framing pulse RSCFS and RSFSn/MRSFS are active high ...
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IDT82V2108 E1 Receive Backplane Parity / F-bit Configuration (012H, 092H, 112H, 192H, 212H, 292H, 312H, 392H) Bit No Bit Name RPTYP RPTYE Type R/W R/W Default 0 0 RPTYP: This bit chooses the parity type for the receive ...
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IDT82V2108 E1 Receive Backplane Time Slot Offset (013H, 093H, 113H, 193H, 213H, 293H, 313H, 393H) Bit No Bit Name TSOFF[6] Type Reserved R/W Default 0 These bits determine the time slot offset between the signal on the RSCFS ...
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IDT82V2108 E1 Transmit Backplane Configuration (018H, 098H, 118H, 198H, 218H, 298H, 318H, 398H) Bit No Bit Name Type Reserved Default TSCKSLV Transmit Clock Master mode is enabled Transmit Clock Slave mode or Transmit Multiplexed ...
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IDT82V2108 E1 Transmit Backplane Frame Pulse Configuration (019H, 099H, 119H, 199H, 219H, 299H, 319H, 399H) Bit No Bit Name Type Default FPINV The positive pulse on the TSCFS pin is valid The negative pulse ...
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IDT82V2108 E1 Transmit Backplane Time Slot Offset (01BH, 09BH, 11BH, 19BH, 21BH, 29BH, 31BH, 39BH) Bit No Bit Name TSOFF[6] Type Reserved R/W Default 0 In Transmit Clock Slave mode, the content in the TSOFF[6:0] determines the time ...
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IDT82V2108 E1 RJAT Interrupt Status (020H, 0A0H, 120H, 1A0H, 220H, 2A0H, 320H, 3A0H) Bit No Bit Name Type Default OVRI: If data is still attempted to write into the FIFO when the FIFO is already full, the overwritten ...
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IDT82V2108 E1 RJAT Configuration (023H, 0A3H, 123H, 1A3H, 223H, 2A3H, 323H, 3A3H) Bit No Bit Name Type Reserved Default CENT: The CENT allows the RJAT FIFO to self-center its read pointer, maintaining the pointer at least 4 UI ...
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IDT82V2108 E1 TJAT Reference Clock Divisor (N1) Control (025H, 0A5H, 125H, 1A5H, 225H, 2A5H, 325H, 3A5H) Bit No Bit Name N1[7] N1[6] Type R/W R/W Default 0 0 These bits define a binary number. The (N1[7: ...
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IDT82V2108 E1 TJAT Configuration (027H, 0A7H, 127H, 1A7H, 227H, 2A7H, 327H, 3A7H) Bit No Bit Name Type Reserved Default CENT: The CENT allows the TJAT FIFO to self-center its read pointer, maintaining the pointer at least 4 UI ...
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IDT82V2108 E1 RHDLC Receive Data Link 1 Control (TXCISEL = 0) (028H, 0A8H, 128H, 1A8H, 228H, 2A8H, 328H, 3A8H) Bit No Bit Name DL1_EVEN DL1_ODD Type R/W R/W Default 0 0 When the TXCISEL (b3, E1-00AH) is ‘0’, ...
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IDT82V2108 E1 RHDLC Receive Data Link 2 Control (TXCISEL = 0) (02AH, 0AAH, 12AH, 1AAH, 22AH, 2AAH, 32AH, 3AAH) Bit No Bit Name DL2_EVEN DL2_ODD Type R/W R/W Default 0 0 When the TXCISEL (b3, E1-00AH) is ‘0’, ...
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IDT82V2108 E1 RHDLC Receive Data Link 3 Control (TXCISEL = 0) (02CH, 0ACH, 12CH, 1ACH, 22CH, 2ACH, 32CH, 3ACH) Bit No Bit Name DL3_EVEN DL3_ODD Type R/W R/W Default 0 0 When the TXCISEL (b3, E1-00AH) is ‘0’, ...
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IDT82V2108 E1 THDLC Transmit Data Link 1 Control (TXCISEL = 1) (028H, 0A8H, 128H, 1A8H, 228H, 2A8H, 328H, 3A8H) Bit No Bit Name DL1_EVEN DL1_ODD Type R/W R/W Default 0 0 When the TXCISEL (b3, E1-00AH) is ‘1’, ...
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IDT82V2108 E1 THDLC Transmit Data Link 2 Control (TXCISEL = 1) (02AH, 0AAH, 12AH, 1AAH, 22AH, 2AAH, 32AH, 3AAH) Bit No Bit Name DL2_EVEN DL2_ODD Type R/W R/W Default 0 0 When the TXCISEL (b3, E1-00AH) is ‘1’, ...
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IDT82V2108 E1 THDLC Transmit Data Link 3 Control (TXCISEL = 1) (02CH, 0ACH, 12CH, 1ACH, 22CH, 2ACH, 32CH, 3ACH) Bit No Bit Name DL3_EVEN DL3_ODD Type R/W R/W Default 0 0 When the TXCISEL (b3, E1-00AH) is ‘1’, ...
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IDT82V2108 E1 FRMP Frame Alignment Options (030H, 0B0H, 130H, 1B0H, 230H, 2B0H, 330H, 3B0H) Bit No Bit Name CRCEN CASDIS Type R/W R/W Default 1 0 CRCEN Disable searching for CRC Multi-Frame Enable searching ...
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IDT82V2108 E1 FRMP Maintenance Mode Options (031H, 0B1H, 131H, 1B1H, 231H, 2B1H, 331H, 3B1H) Bit No Bit Name BIT2C Type Reserved R/W Default 1 BIT2C Out of Basic frame synchronization is declared on 3 consecutive FAS ...
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IDT82V2108 E1 FRMP Framing Status Interrupt Enable (032H, 0B2H, 132H, 1B2H, 232H, 2B2H, 332H, 3B2H) Bit No Bit Name C2NCIWE OOFE Type R/W R/W Default 0 0 C2NCIWE Disable the interrupt on the INT pin when ...
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IDT82V2108 E1 FRMP Maintenance / Alarm Status Interrupt Enable (033H, 0B3H, 133H, 1B3H, 233H, 2B3H, 333H, 3B3H) Bit No Bit Name RAIE RMAIE Type R/W R/W Default 0 0 RAIE Disable the interrupt on the INT ...
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IDT82V2108 E1 FRMP Framing Status Interrupt Indication (034H, 0B4H, 134H, 1B4H, 234H, 2B4H, 334H, 3B4H) Bit No Bit Name C2NCIWI OOFI Type R R Default X X All the bits in this register are clear to ‘0’ after ...
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IDT82V2108 E1 FRMP Maintenance / Alarm Status Interrupt Indication (035H, 0B5H, 135H, 1B5H, 235H, 2B5H, 335H, 3B5H) Bit No Bit Name RAII RMAII Type R R Default X X All the bits in this register are clear to ...
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IDT82V2108 E1 FRMP Framing Status (036H, 0B6H, 136H, 1B6H, 236H, 2B6H, 336H, 3B6H) Bit No Bit Name C2NCIWV OOFV Type R R Default X X C2NCIWV The Frame Processor does not operate in CRC to non-CRC ...
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IDT82V2108 E1 FRMP Maintenance / Alarm Status (037H, 0B7H, 137H, 1B7H, 237H, 2B7H, 337H, 3B7H) Bit No Bit Name RAIV RMAIV Type R R Default X X RAIV: This bit indicates the value of the Remote Alarm Indication ...
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IDT82V2108 E1 FRMP Time Slot 0 International / National Bits (038H, 0B8H, 138H, 1B8H, 238H, 2B8H, 338H, 3B8H) Bit No Bit Name Si[1] Si[0] Type R R Default X X The content in this register reflects the International ...
Page 179
IDT82V2108 E1 FRMP CRC Error Counter-MSB / Time Slot 16 Extra Bits (03AH, 0BAH, 13AH, 1BAH, 23AH, 2BAH, 33AH, 3BAH) Bit No Bit Name OVR NEWDATA Type R R Default 0 0 OVR: Overwritten means that the data ...
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IDT82V2108 E1 FRMP National Bit Codeword Interrupt Enables (03BH, 0BBH, 13BH, 1BBH, 23BH, 2BBH, 33BH, 3BBH) Bit No Bit Name SaSEL[2] SaSEL[1] Type R/W R/W Default 0 0 SaSEL[2:0]: The SaSEL[2:0] select the National Bit Codeword (SaX) to ...
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IDT82V2108 E1 FRMP National Bit Codeword (03DH, 0BDH, 13DH, 1BDH, 23DH, 2BDH, 33DH, 3BDH) Bit No Bit Name Type Default These bits directly reflect the content in the SaX nibble codeword of the CRC Sub Multi-Frame. ‘X’ is ...
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IDT82V2108 E1 FRMP Frame Pulse/Alarm/V5.2 Link ID Interrupt Enables (03EH, 0BEH, 13EH, 1BEH, 23EH, 2BEH, 33EH, 3BEH) Bit No Bit Name OOOFE RAICCRCE Type R/W R/W Default 0 0 OOOFE Disable the interrupt on the INT ...
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IDT82V2108 E1 FRMP Frame Pulse / Alarm Interrupts (03FH, 0BFH, 13FH, 1BFH, 23FH, 2BFH, 33FH, 3BFH) Bit No Bit Name OOOFI RAICCRCI Type R R Default X X The bits of this register are clear to ‘0’ after ...
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IDT82V2108 E1 FRMG Configuration (040H, 0C0H, 140H, 1C0H, 240H, 2C0H, 340H, 3C0H) Bit No Bit Name FRESH SIGEN Type R/W R/W Default 0 1 FRESH Normal operation Initiate the FIFO in the Frame Generator ...
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IDT82V2108 = 1: Ignore the setting in the X[2:0] bits. The value in the extra bits is taken from TSDn/MTSD. E1 FRMG Transmit Alarm / Diagnostic Control (041H, 0C1H, 141H, 1C1H, 241H, 2C1H, 341H, 3C1H) Bit No Bit ...
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IDT82V2108 E1 FRMG International Bits Control (042H, 0C2H, 142H, 1C2H, 242H, 2C2H, 342H, 3C2H) Bit No Bit Name Si[1] Si[0] Type R/W R/W Default 1 1 Si[1:0]: Valid when the FDIS (b3, E1-040H) and the INDIS (b1, E1-040H) ...
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IDT82V2108 E1 FRMG Interrupt Enable (044H, 0C4H, 144H, 1C4H, 244H, 2C4H, 344H, 3C4H) Bit No Bit Name Type Reserved Default SIGMFE Disable the interrupt on the INT pin when the SIGMFI (b4, E1-045H) is logic one. ...
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IDT82V2108 E1 FRMG Interrupt Status (045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H) Bit No Bit Name Type Reserved Default The bits in this register are clear to ‘0 after the register is read. SIGMFI: Valid when the ...
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IDT82V2108 E1 FRMG National Bit Codeword (047H, 0C7H, 147H, 1C7H, 247H, 2C7H, 347H, 3C7H) Bit No Bit Name SaX_EN[1] SaX_EN[2] Type R/W R/W Default 0 0 SaX_ENn: Valid when the FDIS (b3, E1-040H) is logic 0, and the ...
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IDT82V2108 If the EN is set from logic 1 to logic 0 and back to logic 1, the RHDLC will immediately terminate the reception of the current data frame, empty the FIFO buffer, clear the interrupts and initiate a new ...
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IDT82V2108 E1 RHDLC #1, #2, #3 Status (04AH, 0CAH, 14AH, 1CAH, 24AH, 2CAH, 34AH, 3CAH) Bit No Bit Name FE OVR Type R R Default X X Selection of the RHDLC block (#1, #2, or #3) whose registers ...
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IDT82V2108 E1 RHDLC #1, #2, #3 Data (04BH, 0CBH, 14BH, 1CBH, 24BH, 2CBH, 34BH, 3CBH) Bit No Bit Name RD[7] RD[6] Type R R Default X X Selection of the RHDLC block (#1, #2, or #3) whose registers ...
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IDT82V2108 E1 THDLC #1, #2, #3 Configuration (050H, 0D0H, 150H, 1D0H, 250H, 2D0H, 350H, 3D0H) Bit No Bit Name FLGSHARE FIFOCLR Type R/W R/W Default 1 0 Selection of the THDLC block (#1, #2, or #3) whose registers ...
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IDT82V2108 E1 THDLC #1, #2, #3 Upper Transmit Threshold (051H, 0D1H, 151H, 1D1H, 251H, 2D1H, 351H, 3D1H) Bit No Bit Name UTHR[6] Type Reserved R/W Default 1 Selection of the THDLC block (#1, #2, or #3) whose registers ...
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IDT82V2108 E1 THDLC #1, #2, #3 Interrupt Enable (053H, 0D3H, 153H, 1D3H, 253H, 2D3H, 353H, 3D3H) Bit No Bit Name Type Default Selection of the THDLC block (#1, #2, or #3) whose registers are visible on the microprocessor ...
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IDT82V2108 E1 THDLC #1, #2, #3 Interrupt Status / UDR Clear (054H, 0D4H, 154H, 1D4H, 254H, 2D4H, 354H, 3D4H) Bit No Bit Name FULL Type Reserved R Default X Selection of the THDLC block (#1, #2, or #3) ...
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IDT82V2108 E1 THDLC #1, #2, #3 Transmit Data (055H, 0D5H, 155H, 1D5H, 255H, 2D5H, 355H, 3D5H) Bit No Bit Name TD[7] TD[6] Type R/W R/W Default X X Selection of the THDLC block (#1, #2, or #3) whose ...
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IDT82V2108 E1 RPLC Configuration (05CH, 0DCH, 15CH, 1DCH, 25CH, 2DCH, 35CH, 3DCH) Bit No Bit Name Type Default PCCE The per-TS functions in RPLC are disabled The per-TS functions in RPLC are enabled. E1 ...
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IDT82V2108 E1 RPLC Channel Indirect Data Buffer (05FH, 0DFH, 15FH, 1DFH, 25FH, 2DFH, 35FH, 3DFH) Bit No Bit Name D7 D6 Type R/W R/W Default 0 0 This register hold the value which will be read from or ...
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IDT82V2108 20H ~ 3FH 40H ~ 5FH 61H ~ 7FH E1 RPLC Per-TS Configuration Registers (RPLC Indirect Registers 20H ~ 3FH) Bit No Bit Name TEST DTRKC/NxTS Type R/W R/W Default X X TEST Disable the ...