IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 228

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
T1 / J1 Data Link Micro Select / Framer Reset (00DH, 08DH, 10DH, 18DH, 20DH, 28DH, 30DH, 38DH)
RHDLCSEL[1:0]:
the HDLC link position is fixed in the DL of F-bit. When RHDLC #2 is selected, the microprocessor will access the HDLC #2 controller to assign the link
to any one of 24 channels. These bits must be set before using the HDLC controller.
THDLCSEL[1:0]:
selected, the HDLC link position is fixed in the DL of F-bit. When THDLC #2 is selected, the microprocessor will access the HDLC #2 controller to
assign the link to any one of 24 channels. These bits must be set before using the HDLC controller.
TXCISEL:
extracted bit in the received data stream and the inserted bit in the transmitting data stream respectively. This bit is used to decide whether the Read/
Write operation on the registers addressed from T1/J1-070H to T1/J1-071H is for the HDLC receiver or for the HDLC transmitter.
RESET:
to bring the framer out of reset. Holding the framer in a reset state effectively puts it into a low power standby mode. A hardware reset clears the
RESET bit and the bits in this register.
Programming Information
Bit Name
Default
Bit No.
Type
The RHDLCSEL[1:0] select one of the two HDLC Receivers to be accessed by the microprocessor in ESF format. When RHDLC #1 is selected,
The THDLCSEL[1:0] select which one of the two HDLC Transmitters to be accessed by the microprocessor in ESF format. When THDLC #1 is
The registers addressed from T1/J1-070H to T1/J1-071H are shared by the HDLC Receiver and HDLC Transmitter to decide the position of the
= 0: The Read/Write operation on registers addressed from T1/J1-070H to T1/J1-071H is for HDLC receiver.
= 1: The Read/Write operation on registers addressed from T1/J1-070H to T1/J1-071H is for the HDLC transmitter.
This bit implements a software reset for individual framer.
= 0: Normal operation.
= 1: The corresponding framer is held in reset. However, this bit and the bits in this register can not be reset. Therefore, a logic 0 must be written
RHDLCSEL[1]
R/W
X
7
RHDLCSEL[0]
R/W
X
6
THDLCSEL[1]
THDLCSEL[1:0]
RHDLCSEL[1:0]
R/W
X
5
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
THDLCSEL[0]
R/W
X
4
218
HDLC Transmitter
HDLC Receiver
RHDLC #1
RHDLC #2
Reserved
THDLC #1
THDLC #2
Reserved
TXCISEL
R/W
X
3
2
Reserved
T1 / E1 / J1 OCTAL FRAMER
1
March 5, 2009
RESET
R/W
0
0