IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 31

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
3.4
Yellow signal and the AIS (Blue Alarm) signal in SF/ESF in T1/J1 data
stream and declares the Yellow alarm, the Red alarm and the AIS alarm.
The T1 or J1 mode is selected by the J1_YEL (b5, T1/J1-02CH) while
the SF or ESF format is selected by the ESF (b4, T1/J1-02CH).
channel. When the occurrence of logic 1 in this bit position is less than
16 times (including 16 times) during a 40 ms period, the Yellow signal is
declared.
frame. When the occurrence of logic 0 on this bit position is less than 2
times (including 2 times) during a 40 ms period, the Yellow signal is
declared.
bit (refer to Table 4). The pattern is ‘FF00’ in T1 mode and ‘FFFF’ in J1
mode. When the AVC (b1, T1/J1-02AH) is logic 0, the Yellow signal is
declared if 8 out of 10 successive patterns match the ‘FF00’ (in T1) or
‘FFFF’ (in J1) on the DL bit position. When the AVC (b1, T1/J1-02AH) is
logic 1, the Yellow signal is declared if 4 out of 5 successive patterns
match the ‘FF00’ (in T1) or ‘FFFF’ (in J1) on the DL bit position.
Table 7: Alarm Summary in ALMD
Functional Description
Yellow Alarm
Red Alarm
AIS Alarm
The Alarm Detector block exists in T1/J1 mode only. It detects the
The Yellow signal is declared differently in each format:
- In T1 SF format: The Yellow signal occupies the 2nd bit of each
- In J1 SF format: The Yellow signal occupies the F-bit of the 12th
- In T1/J1 ESF format: The Yellow signal occupies the DL of the F-
ALARM DETECTOR (ALMD) - T1/J1 ONLY
the Yellow signal is present for 425 ms (± 50 ms)
the Red signal is present for 2.55 sec (± 40 ms)
the AIS signal is present for 1.5 sec (± 100 ms)
Declaring
the Red signal is absent for 16.6 sec (± 500 ms); or the Red signal is absent for 120 ms if the
the AIS signal is absent for 16.8 sec (± 500 ms); or the AIS signal is absent for 180 ms if the
21
J1-02FH).
synchronization for 60 ms and the received logic 0 is less than 127 times
in the same period. Then the AIS signal will be indicated by the AISD
(b0, T1/J1-02FH).
event occurs in 40 ms. Then the Red signal will be indicated by the
REDD (b2, T1/J1-02FH).
cleared when the corresponding alarm signal is present or absent for a
certain period as summarized in Table 7.
sources in the ALMD block. When the alarm occurs, the corresponding
Interrupt Status Register (YEL, AIS or RED in b2, b0, b1 of T1/J1-02EH
respectively) will indicate the alarm. When there is any transition (from
‘0’ to ‘1’ or from ‘1’ to ‘0’) on the Interrupt Status Register, its correspond-
ing Interrupt Indication Register (YELI, AISI or REDI in b5, b3, b4 of T1/
J1-02EH respectively) will be logic 1. A transition on the Interrupt Indica-
tion Register can cause an interrupt on the INT pin if the corresponding
Interrupt Enabled Register (YELE, AISE or REDE in b2, b0, b1 of T1/J1-
02DH respectively) is logic 1.
Any of the above conditions will be indicated by the YELD (b1, T1/
The AIS signal is declared when the received data is out of SF/ESF
The Red signal is declared when one or more out of SF/ESF sync
The Yellow alarm, AIS alarm and Red alarm will be declared or
The Yellow alarm, AIS alarm and Red alarm are also the interrupt
the Yellow signal is absent for 425 ms (± 50 ms)
FASTD (b4, T1/J1-02DH) is set
FASTD (b4, T1/J1-02DH) is set
Clearing
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009