IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 218

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
T1 / J1 Receive Side System Interface Options (001H, 081H, 101H, 181H, 201H, 281H, 301H, 381H)
IMODE[1:0]:
in the RSCKn clock pulse.
those un-selected channels. The selection of the channel is decided by the EXTRACT (b2, T1/J1-RPLC-Indirect Register-01-18 H).
uated version of LRCKn or an 8KHz clock.
data. Each channel signaling data is channel aligned with the RSDn data stream and located in lower nibble (b5b6b7b8) of the time slot.
RSCKSEL:
RSCCK2M, RSCCK8M:
is configured in Receive Clock Slave mode. If the Receive Multiplexed mode is desired, all the RSCCK2M & RSCCK8M in eight framers must be set
the same to select the 8.192 Mbit/s backplane bit rate. When the RSCCK2M, RSCCK8M selects the 8.192 Mbit/s, the IMODE[1:0] (b7~6, T1/J1-001H)
must be set to ‘11’.
Programming Information
Bit Name
Default
Bit No.
These bits select the operation mode in the receive path.
‘Receive Clock Master Full T1/J1’ mode means that the received entire frame (193 bits) is clocked out from the RSDn pin, and there are no gaps
‘Receive Clock Master Fractional T1/J1’ mode means that RSCKn only clocks out on the selected channels, and RSCKn does not pulse during
When Receive Clock Slave RSCK Reference Mode is enabled, the RSCKn/RSSIGn pin will be used as RSCKn to output a 1.544 MHz jitter atten-
When Receive Clock Slave External Signaling mode is enabled, the RSCKn/RSSIGn pin is used as RSSIGn to output the extracted signaling
When Receive Clock Slave RSCK Reference Mode is enabled, this bit selects the frequency of RSCKn.
= 0: RSCKn outputs an 8 KHz timing reference that is generated by dividing the jitter attenuated version of LRCKn.
= 1: RSCKn outputs a jitter attenuated version of the 1.544MHz receive line clock (LRCK).
These bits determine the bit rate of the received data stream on the backplane. The 2.048 Mbit/s rate can only be supported when the backplane
Type
IMODE[1]
R/W
7
1
IMODE[0]
R/W
6
1
IMODE[1:0]
RSCCK2M, RSCCK8M
0 0
0 1
1 0
1 1
RSCKSEL
0 0
1 0
0 1
1 1
R/W
5
0
Receive Clock Slave External Signaling mode
Receive Clock Master Fractional T1/J1 mode
Receive Clock Slave RSCK Reference mode
Receive Clock Master Full T1/J1 mode
Operation Mode In Receive Path
RSCCK2M
R/W
4
0
208
RSCCK8M
Backplane Rate
R/W
1.544M bit/s
2.048M bit/s
8.192M bit/s
3
0
Reserved
RSFSP
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
ALTIFP
R/W
1
0
March 5, 2009
IMTKC
R/W
0
0