IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 74

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
Functional Description
MTSCCKB
MTSCCKB
MTSSIG
LTCK n
MTSCFS
MTSSIG
LTDn
MTSCFS
MTSD
LTCKn
MTSD
LTDn
Line Interface (of any of the Framer1 to Framer4):
Line Interface (of any of the Framer1 to Framer4):
D
D
X
1
X
1
X
X
2
2
TS31-7
X
3
X
3
TS31-7
4
X
4
X
Framer1_TS31
A
Framer1_TS31
A
5
5
6
B
Figure 46. E1 Transmit Multiplexed Mode - Functional Timing Example 1
Figure 47. E1 Transmit Multiplexed Mode - Functional Timing Example 2
6
B
C
TS31-8
7
C
7
TS31-8
8
D
8
D
X
The FE (b3, E1-018H) is logic 1 and the DE (b4, E1-018) is logic 0. The COFF (b4, E1-01CH) is in its default value.
X
TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011, the CHI and the
1
1
The TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001, the
X
2
X
2
The TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001,
In this example, Framer1 to Framer4 are supposed to be demultiplexed from one multiplexed bus.
the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to 7'b0000011,
TS0-1
3
X
In this example, Framer1 to Framer4 are supposed to be demultiplexed from one multiplexed bus.
3
X
Framer1_TS0
TS0-1
Framer1_TS0
X
4
X
4
The CMS (b2, E1-018H) is logic 1, i.e., the bankplane clock rate is 16.384Mbit/s.
A
5
The CMS (b2, E1-018H) is logic 0, i.e., the bankplane clock rate is 8.192Mbit/s.
A
5
6
B
B
6
The FE (b3, E1-018H) is logic 0 and the DE (b4, E1-018) is logic 0.
the CHI and the BOFF[2:0] of the four Framers are set to logic 0:
C
7
TS0-2
C
7
TS0-2
BOFF[2:0] of the four Framers are set to logic 0:
8
D
8
D
X
1
X
1
2
X
2
X
3
TS0-3
X
3
X
TS0-3
X
4
4
X
64
Framer2_TS0
Framer2_TS0
A
5
A
5
B
6
B
6
C
TS0-4
7
C
7
TS0-4
8
D
8
D
X
1
X
1
2
X
X
2
3
X
TS0-5
3
X
TS0-5
4
X
4
X
5
A
Framer3_TS0
5
A
Framer3_TS0
6
B
6
B
7
C
7
C
TS0-6
TS0-6
8
D
8
D
1
X
1
X
T1 / E1 / J1 OCTAL FRAMER
X
2
X
2
3
X
3
X
TS0-7
TS0-7
4
X
X
4
A
5
A
5
Framer4_TS0
Framer4_TS0
B
6
B
6
March 5, 2009
C
7
C
7
TS0-8
TS0-8
D
8
D
8
1
1