IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 263

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
T1 / J1 RPLC Per-Channel Configuration Registers (RPLC Indirect Registers 01H ñ 18H)
INVERT:
output from the RSDn/MRSD pin.
DTRKC:
RSDn/MRSD pin.
RSDn/MRSD pin.
DMW:
SIGNINV:
TEST:
the test pattern from PRGD to replace the data in the corresponding channel for test (when the RXPATGEN [b2, T1/J1-00FH] is logic 1).
Similarly, all channels set to be replaced with PRGD test pattern data are concatenated replaced by the PRBS.
EXTRACT:
Programming Information
Bit Name
Default
Bit No.
Type
This bit, together with the SIGNINV (b4, T1/J1-RPLC-indirect register - 01~18H), determines the bit inversion of the corresponding channel when
= 0: Disable the data in the corresponding channel to be replaced by the data set in the DTRK[7:0] (b7~0, T1/J1-19~30H) when output on the
= 1: Enable the data in the corresponding channel to be replaced by the data set in the DTRK[7:0] (b7~0, T1/J1-19~30H) when output on the
= 0: Disable the data in the corresponding channel to be replaced with a digital milliwatt pattern when output on the RSDn/MRSD pin.
= 1: Enable the data in the corresponding channel to be replaced with a digital milliwatt pattern when output on the RSDn/MRSD pin.
Refer to the INVERT (b7, T1/J1-RPLC-indirect register - 01~18H)
= 0: Disable the data in the corresponding channel to be tested by PRGD.
= 1: Enable the data in the corresponding channel to be extracted to PRGD for test (when the RXPATGEN [b2, T1/J1-00FH] is logic 0), or enable
All the channels that are extracted to the PRGD are concatenated and treated as a continuous stream in which pseudo random is searched for.
This bit is valid in Receive Clock Slave Fractional T1/J1 mode:
= 0: RSCKn is held in its inactivated state.
= 1: RSCKn is clocked for the corresponding channel.
INVERT
R/W
X
7
INVERT
0
0
1
1
DTRKC
R/W
6
X
SIGNINV
01H ~ 18H
19H ~ 30H
31H ~ 48H
0
1
0
1
DMW
R/W
X
5
RPLC Indirect Registers Map
Data Trunk Conditioning Code for Channel 1 ~ 24
Signaling Trunk Conditioning for Channel 1 ~ 24
Invert all the bits except the MSB of the corresponding channel
Per-Channel Configuration for Channel 1 ~ 24
SIGNINV
R/W
X
4
Invert all the bits of the corresponding channel
Invert the MSB of the corresponding channel
253
No bit inversion
Bit Inversion
TEST
R/W
X
3
EXTRACT
R/W
2
X
T1 / E1 / J1 OCTAL FRAMER
R/W
FIX
X
1
March 5, 2009
POL
R/W
X
0