IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 75

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
3.13.1.4
in the previous Basic Frame and the result is inserted into the first bit
(MSB) of TS0 on the TSDn/MTSD pin. The even parity or odd parity is
chosen by the TPTYP (b7, E1-01AH) and whether the first bit of TS0 is
calculated or not is determined by the PTY_EXTD (b3, E1-01AH). The
parity error event will be captured by the TDI (b5, E1-01AH). The parity
error will cause an interrupt on the INT pin if the TPTYE (b6, E1-01AH) is
enabled.
3.13.1.5
time slot offset is enabled by setting a non-zero value into the
TSOFF[6:0] (b6~0, E1-01BH). The time slot offset is between TSCFS/
MTSCFS and the start of the corresponding frame to be transmitted on
TSDn/MTSD. The time slot offset can be set in both single clock mode
(CMS [b2, E1-018H] = 0) and double clock mode (CMS [b2, E1-018H] =
1).
zero value into the BOFF[2:0] (b2~0, E1-01CH). In the Transmit Clock
Functional Description
In all the above four modes, parity check is calculated over the bits
In the Transmit Clock Slave mode and Transmit Multiplexed mode,
In all the above four modes, bit offset is enabled by setting a non-
Parity Check
Offset
TSCCKB
TSCFS
TSDn
TSDn
The CHI (b3, E1-01CH) = 0 and the bit offset is 0:
The bit offset is set as: CHI (b3, E1-01CH) = 0, BOFF[2:0] (b2~0, E1-01CH) = 010; i.e. 2-bit offset:
For example: in Transmit Clock Slave mode, CMS (b2, E1-018H) = 0, DE (b4, E1-018H) = 0, FE (b3, E1-018H) = 0:
1
2
3
1
TS31
4
2
Figure 48. Transmit Bit Offset in E1 Mode - 1
5
3
TS31
6
4
7
5
8
6
1
7
65
8
2
Slave mode and Transmit Multiplexed mode, the bit offset is between
TSCFS/MTSCFS and the start of the corresponding frame to be trans-
mitted on TSDn/MTSD. The bit offset can be set in both single clock
mode (CMS [b2, E1-018H] = 0) and double clock mode (CMS [b2, E1-
018H] = 1). However, if the CHI (b3, E1-01CH) is logic 0, the bit offset
value equals the setting in the BOFF[2:0] (b2~0, E1-01CH). That is,
‘000’ in the BOFF[2:0] (b2~0, E1-01CH) means no bit offset; ‘001’ in the
BOFF[2:0] (b2~0, E1-01CH) means one bit offset, and so on (refer to the
examples in Figure 48 and Figure 49). If the CHI (b3, E1-01CH) is logic
1, the bit offset configured in the BOFF[2:0] (b2~0, E1-01CH) meets the
Concentration Highway Interface (CHI) specification (refer to Table 31
and Table 32). The CER (clock edge receive) is counted from the active
edge of TSCFS/MTSCFS (refer to the examples in Figure 50 and
Figure 51). When the bit offset is configured, the signal on TSSIGn/
MTSSIG or the pulse on TSFSn is aligned to RSDn/MRSD. In Transmit
Clock Master mode, the bit offset is between TSFSn and the start of the
corresponding frame to be transmitted on TSDn. In this case, the CHI
specification is not supported and the bit offset value equals the setting
in the BOFF[2:0] (b2~0, E1-01CH) (refer to the example in Figure 52).
1
3
4
2
TS0
5
3
6
4
TS0
7
5
8
6
1
7
2
8
T1 / E1 / J1 OCTAL FRAMER
TS2
3
1
4
2
TS2
3
4
March 5, 2009