IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 245

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
ZCS[1:0]:
pattern generated in the PRGD; Replace the data with the value in the IDLE[7:0]; Invert the bit.
T1 / J1 TPLC IDLE Code Byte Registers (TPLC Indirect Registers 19H ~ 30H)
T1 / J1 TPLC Signaling Control Byte Registers (TPLC Indirect Registers 31H ~ 48H)
SIGC0:
SIGC1:
A, B, C, D:
Programming Information
ZCS[1:0]
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
0 0
0 1
1 0
1 1
Type
Type
The priority of the TPLC operation on the TSDn/MTSD pin from high to low is:
Extract data to PRGD for test; Zero Code Suppression; Payload loopback; Replace the data with the milliwatt pattern; Replace the data with the
They contain the data that will replace the data input from the TSDn/MTSD pin when the corresponding IDLE_DS0 is logic 1. IDLE7 is the MSB.
This bit is valid when the corresponding SIGC1 is logic 1.
= 0: Use the data input from the TSSIGn/MTSSIG pin as the signaling.
= 1: Use the data in the A, B, C, D as the signaling.
= 0: Disable replacing the signaling bit with the data input from the TSSIGn/MTSSIG pin or the data in the A, B, C, D.
= 1: Enable replacing the signaling bit with the data input from the TSSIGn/MTSSIG pin or the data in the A, B, C, D.
They contain the data that can be used as signaling when the corresponding SIGC0 is logic 1. They are in the least significant nibble.
No zero code suppression.
Every bit 8 in the corresponding channel is forced to be logic one.
GTE Zero Code Suppression - Every bit 8 (or bit 7 in signaling frames) is forced to be logic one when the bits in the corresponding channel are all ‘Zero’s.
Bell Zero Code Suppression - Every bit 7 is forced to be logic one when the bits in the corresponding channel are all ‘Zero’s.
SIGC0
IDLE7
R/W
R/W
X
X
7
7
SIGC1
IDLE6
R/W
R/W
6
X
6
X
IDLE5
R/W
X
5
5
Reserved
Per-Channel Zero Code Suppression
IDLE4
R/W
X
4
4
235
IDLE3
R/W
R/W
X
A
X
3
3
IDLE2
R/W
R/W
2
X
2
B
X
T1 / E1 / J1 OCTAL FRAMER
IDLE1
R/W
R/W
X
C
X
1
1
March 5, 2009
IDLE0
R/W
R/W
X
D
X
0
0