IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 147

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
E1 Diagnostics (007H, 087H, 107H, 187H, 207H, 287H, 307H, 387H)
LINELB:
and clock (LRDn and LRCKn). The loop back data stream can pass through the Receive Jitter Attenuator or bypass the Receive Jitter Attenuator (if
the Receive Jitter Attenuator is configured to be bypassed).
V52DIS:
controllers are disabled.
DDLB:
(LTDn and LTCKn) without the Receive Jitter Attenuator.
RAIS:
nal Signaling mode. In Receive Multiplexed mode, the data of the corresponding framer output on MRSD is forced to be all ‘One’s, and the signal of
the corresponding framer output on MRSSIG is frozen at the current valid signaling.
TXDIS:
Programming Information
Bit Name
Default
Bit No.
Type
Line Loopback means that the transmit line interface data and clock (LTDn and LTCKn) are internal directly comes from the received line data
= 0: Line loop back is disabled.
= 1: Line loop back is enabled.
= 0: All HDLC controllers of the corresponding framer are available to use.
= 1: Only the first HDLC controller in receive direction (RHDLC#1) and transmit direction (THDLC#1) is available to use, the remaining HDLC
Note that this bit can not be reset by software reset. It can only be reset by hardware reset.
Digital Loopback means that the received line data and clock (LRDn and LRCKn) are internal directly comes from the transmit line data and clock
= 0: Digital loop back is disabled.
= 1: Digital loop back is enabled.
= 0: normal operation.
= 1: Force the data output on RSDn to be all ‘One’s, and freeze the signal on RSSIGn at the current valid signaling in Receive Clock Slave Exter-
= 0: normal transmission.
= 1: Force the data to be transmitted on the TLDn pin to be all ‘Zero’s.
7
Reserved
6
5
LINELB
R/W
4
0
137
V52DIS
R/W
3
0
DDLB
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
RAIS
R/W
1
0
March 5, 2009
TXDIS
R/W
0
0