IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 185

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
E1 FRMG Transmit Alarm / Diagnostic Control (041H, 0C1H, 141H, 1C1H, 241H, 2C1H, 341H, 3C1H)
MTRK:
signaling; when the SIGEN (b6, E1-040H) is logic 0, replace the data on TS16 with IDLE code.
FPATINV:
SPLRINV:
SPATINV:
REMAIS:
MFAIS:
TS16AIS:
AIS:
Programming Information
Bit Name
Default
Bit No.
Type
= 1: Ignore the setting in the X[2:0] bits. The value in the extra bits is taken from TSDn/MTSD.
Valid when the FDIS (b3, E1-040H) is logic 0 and the PCCE (b0, E1-060H) is logic 1.
= 0: Ignore the setting in the IDLE Code Byte register.
= 1: Replace the data on TS1~15 & TS17~31 with the IDLE code. And when the SIGEN (b6, E1-040H) is logic 1, replace the data on TS16 with
Valid when the FDIS (b3, E1-040H) is logic 0.
= 0: Disable the inversion of the FAS.
= 1: Enable the inversion of the FAS (from ‘0011011’ to ‘1100100’).
Valid when the FDIS (b3, E1-040H) is logic 0.
= 0: Disable the inversion of the 2nd bit of NFAS.
= 1: Enable the inversion of the 2nd bit of NFAS (from ‘1’ to ‘0’).
Valid when the FDIS (b3, E1-040H) is logic 0 and the SIGEN (b6, E1-040H) & the DLEN (b5, E1-040H) are logic 1.
= 0: Disable the inversion of the Signaling Multi-Frame alignment signal.
= 1: Enable the inversion of the Signaling Multi-Frame alignment signal (from ‘0000’ to ‘1111’).
Valid when the FDIS (b3, E1-040H) is logic 0.
= 0: Normal operation.
= 1: Force the 3rd bit of NFAS to be logic 1.
Valid when the FDIS (b3, E1-040H) is logic 0.
= 0: Normal operation.
= 1: Force to transmit the ‘Y’ bit as logic 1.
Valid when the FDIS (b3, E1-040H) is logic 0 and Signaling Multi-Frame generator is enabled.
= 0: Normal transmission.
= 1: Force to transmit all ‘One’s in TS16 unconditionally.
= 0: Normal transmission.
= 1: Force to transmit all ‘One’s on all time slots unconditionally.
MTRK
R/W
7
0
FPATINV
R/W
6
0
SPLRINV
R/W
5
0
SPATINV
R/W
4
0
175
REMAIS
R/W
3
0
MFAIS
R/W
2
0
T1 / E1 / J1 OCTAL FRAMER
TS16AIS
R/W
1
0
March 5, 2009
R/W
AIS
0
0