IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 121

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
Table 52: Various Operation Modes in Receive Path for Reference (Continued)
Table 53: Various Operation Modes in Transmit Path for Reference
Operation
Note:
1. In the ‘Register’ column, except for the Receive/Transmit Multiplexed mode, the register position of Framer 1 is listed to represent the set of the registers of eight framers. The other
registers positions are tabulated in the ‘Register Map’. However, in the Receive/Transmit Multiplexed mode, the registers positions of eight framers are all listed.
2. The ‘Description’ illustrates the fundamental function of the operation mode. The others can be configured as desired.
Signaling Mode
Signaling Mode
Transmit Clock
Transmit Clock
Transmit Clock
Slave External
Slave External
Receive Multi-
(1.544 Mbit/s)
(2.048 Mbit/s)
Enable Mode
plexed Mode
Slave TSFS
(Continued)
Mode
Mode
Register
Register
01BH
01BH
01AH
01BH
004H
005H
044H
007H
004H
005H
044H
007H
004H
005H
044H
007H
019H
02CH
0ACH
12CH
1ACH
22CH
2ACH
32CH
3ACH
0C0H
1C0H
2C0H
3C0H
040H
140H
240H
340H
1
1
Value (from Bit7 to Bit0)
Value (from Bit7 to Bit0)
00001000
10000000
00010000
00001101
00010000
00001000
11000000
00010000
00001101
00010000
00001000
11000100
00010000
00001101
11000000
00010000
11111111
00010000
00010000
00010000
00010000
00010000
00010000
00010000
00010000
00000100
00000100
00000100
00000100
00000100
00000100
00000100
00000100
TSFSn is updated on the falling edge of TSCCKB.
In the Transmit Clock Slave TSFS Enabled mode. The backplane rate is 1.544 Mbit/s.
TSCCKB is selected as the TJAT input reference clock. Smoothed clock is selected as Line Transmit
Clock (LTCK).
The FIFO is set to self-center its read pointer.
In the Transmit Clock Slave External Signaling mode. The backplane rate is 1.544 Mbit/s.
TSCCKB is selected as TJAT input reference clock. Smoothed clock is selected as Line Transmit
Clock (LTCK).
The FIFO is set to self-center its read pointer.
In the Transmit Clock Slave External Signaling mode. The backplane rate is 2.048 Mbit/s.
TSCCKB is selected as the TJAT input reference clock. Smoothed clock is selected as Line Transmit
Clock (LTCK).
Set the Reference Clock Divisor(N1) to ‘255’.
Set the Output Clock Divisor(N2) to ‘192’.
The FIFO is set to self-center its read pointer.
The data on the TSDn and TSCFS pins is sampled on the falling edge of TSCCKB. The data on
The Frame Generator is set in the ESF format.
The data on the TSDn, TSSIGn and TSCFS pins is sampled on the falling edge of TSCCKB.
The Frame Generator is set in the ESF format.
The data on the TSDn, TSSIGn and TSCFS pins is sampled on the falling edge of TSCCKB.
The Frame Generator is set in the ESF format.
The Alarm Detector is set in the ESF format.
The Receive CAS/RBS Buffer is set in the ESF format.
111
Description
Description
2
2
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009