IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 8

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
T1 / E1 / J1 OCTAL FRAMER
Table 49: Error Insertion ............................................................................................................................................................................................ 106
Table 50: Default Setting in Receive Path in T1/J1 Mode ......................................................................................................................................... 108
Table 51: Default Setting in Transmit Path in T1/J1 Mode ........................................................................................................................................ 108
Table 52: Various Operation Modes in Receive Path for Reference ......................................................................................................................... 109
Table 53: Various Operation Modes in Transmit Path for Reference ........................................................................................................................ 111
Table 54: Example for Using HDLC Receiver ........................................................................................................................................................... 116
Table 55: Example for Using HDLC Transmitter ....................................................................................................................................................... 118
Table 56: Test Pattern in T1/J1 Mode ....................................................................................................................................................................... 119
Table 57: Setting of PRGD ........................................................................................................................................................................................ 120
Table 58: Initialization of TPLC .................................................................................................................................................................................. 120
Table 59: Initialization of RPLC ................................................................................................................................................................................. 121
Table 60: Error Insertion ............................................................................................................................................................................................ 122
Table 61: T1/J1 Mode Selection Register .................................................................................................................................................................. 124
Table 62: E1 Mode Register Map - Direct Register ................................................................................................................................................... 124
Table 63: E1 Mode Register Map - Indirect Register ................................................................................................................................................. 127
Table 64: T1/J1 Mode Register Map - Direct Register .............................................................................................................................................. 127
Table 65: T1/J1 Mode Register Map - Indirect Register ............................................................................................................................................ 130
Table 66: IR Code ...................................................................................................................................................................................................... 269
Table 67: IDR ............................................................................................................................................................................................................. 270
Table 68: Boundary Scan Sequence & I/O Pad Cell Type ........................................................................................................................................ 270
Table 69: TAP Controller State Description ............................................................................................................................................................... 273
March 5, 2009
List of Tables
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