IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 244

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
T1 / J1 TPLC Per-Channel Control Registers (TPLC Indirect Registers 01H ~ 18H)
INVERT:
input from the TSDn/MTSD pin.
IDLE_DS0:
DMW:
SIGNINV:
TEST:
the test pattern from PRGD to replace the data in the corresponding channel for test (when the RXPATGEN [b2, T1/J1-00FH] is logic 0).
Similarly, all time slots set to be replaced with PRGD test pattern data are concatenated replaced by the PRBS.
LOOP:
data to be transmitted. When Receive Clock Slave modes are enabled, the Elastic Store is unavailable to facilitate the payload loopbacks, and loop-
back functionality is provided only when the transmit path is also in Transmit Clock Slave mode, and the received clock and the clock to be transmitted
and Common Frame Pulse are identical (RSCCK = TSCCKB, RSCFS = TSCFS).
Programming Information
Bit Name
Default
Bit No.
Type
This bit, together with the SIGNINV (b4, T1/J1-TPLC-indirect register - 01~18H), determines the bit inversion of the corresponding channel when
= 0: Disable the data in the corresponding channel to be replaced by the data set in the IDLE[7:0] when input from the TSDn/MTSD pin.
= 1: Enable the data in the corresponding channel to be replaced by the data set in the IDLE[7:0] when input from the TSDn/MTSD pin.
= 0: Disable the data in the corresponding channel to be replaced with a digital milliwatt pattern when input from the TSDn/MTSD pin.
= 1: Enable the data in the corresponding channel to be replaced with a digital milliwatt pattern when input from the TSDn/MTSD pin.
Refer to the INVERT (b7, T1/J1-TPLC-indirect register - 01~18H).
= 0: Disable the data in the corresponding channel to be tested by PRGD.
= 1: Enable the data in the corresponding channel to be extracted to PRGD for test (when the RXPATGEN [b2, T1/J1-00FH] is logic 1), or enable
All the time slots that are extracted to the PRGD are concatenated and treated as a continuous stream in which pseudo random is searched for.
= 0: Disable the payload loopback.
= 1: Enable the payload loopback. When Receive Clock Master modes are enabled, the Elastic Store is used to align the receive line data to the
INVERT
R/W
X
7
INVERT
0
0
1
1
IDLE_DS0
R/W
6
X
01H ~ 18H
19H ~ 30H
31H ~ 48H
SIGNINV
0
1
0
1
DMW
R/W
X
5
TPLC Indirect Registers Map
Invert all the bits except the MSB of the corresponding channel
SIGNINV
Invert all the bits of the corresponding channel
Invert the MSB of the corresponding channel
R/W
Signaling Control Byte for Channel 1 ~ 24
X
Per-Channel Control for Channel 1 ~ 24
4
234
IDLE Code Byte for Channel 1 ~ 24
No bit inversion
Bit Inversion
TEST
R/W
X
3
LOOP
R/W
2
X
T1 / E1 / J1 OCTAL FRAMER
ZCS[1]
R/W
X
1
March 5, 2009
ZCS[0]
R/W
X
0