IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 54

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
3.11.2
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the RSDn pin is used to output the received data from each framer at a
bit rate of 1.544 Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the
Multiplexed Mode, the received data from the eight framers is converted
to 2.048 Mb/s format and byte-interleaved to form two high speed data
streams and outputs on the MRSD1 and MRSD2 pins at a bit rate of
8.192 Mb/s.
on the RSDn pin is provided by the system side and shared by all eight
framers, the Receive System Interface should be set in Receive Clock
Slave mode. If the timing signal for clocking data on each RSDn pin is
received from each line side, the Receive System Interface should be
set in Receive Clock Master mode.
RSSIGn is used to output a reference clock, the Receive System Inter-
Table 20: T1/J1 Mode Receive System Interface in Different Operation Modes
Table 21: Operation Mode Selection in T1/J1 Receive Path
Functional Description
Note:
* When the RSCCK2M / RSCCK8M are '00', the system clock rate is 1.544MHz.
When the RSCCK2M / RSCCK8M are '10', the system clock rate is 2.048MHz, i.e., T1/J1 mode E1 rate.
Non-Multiplexed
RSCCK2M / RSCCK8M (b4, T1/J1-001H) / (b3, T1/J1-001H)
In T1/J1 mode, the Receive System Interface can be set in Non-
In the Non-multiplexed Mode, if the timing signal for clocking data
In the Receive Clock Slave mode, if the multi-function pin RSCKn/
Mode
T1/J1 MODE
01 (in any of the eight framers)
Clock Master Mode
Clock Slave Mode
Multiplexed Mode
Operation Mode
00 / 10 *
00
External Signaling
RSCK Reference
Fractional T1/J1
Full T1/J1
Data Pin
MRSD
RSDn
RSDn
RSDn
RSDn
IMODE[1:0] (b7~6, T1/J1-001H)
44
face is in Receive Clock Slave RSCK Reference Mode. If the RSCKn/
RSSIGn pin is used to output the extracted signaling bits, the Receive
System Interface is in Receive Clock Slave External Signaling mode.
2.048 MHz in T1/J1 mode, can only be supported in the Receive Clock
Slave mode.
a T1/J1 basic frame is clocked out by RSCKn, the Receive System Inter-
face is in Receive Clock Master Full T1/J1 mode. If the data in only
some time slots of a T1/J1 frame is clocked out by RSCKn, the Receive
System Interface is in Receive Clock Master Fractional T1/J1 Mode.
ating modes. To set the receive system interface of each framer into var-
ious operating modes, the registers must be configured as Table 21.
Clock Pin
10
01
00
11
11
MRSCCK
RSCCK
RSCCK
RSCKn
RSCKn
The T1/J1 mode E1 rate, which means the system clock rate is
In the Receive Clock Master mode, if the data in all 24 channels of
Table 20 summarizes the receive system interface in different oper-
MRSCFS/MRSFS
RSCFS/RSFSn
RSCFS/RSFSn
Framing Pin
RSFSn
RSFSn
Receive Clock Slave External Signaling
Receive Clock Slave RSCK Reference
Receive Clock Master Fractional T1/J1
Receive Clock Master Full T1/J1
Signaling Pin
Receive Multiplexed
MRSSIG
Operation Mode
T1 / E1 / J1 OCTAL FRAMER
RSSIGn
No
No
No
Reference Clock Pin
March 5, 2009
RSCKn
No
No
No
No