IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 17

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
Pin Description
RSFS[1] / MRSFS[1]
RSFS[2] / MRSFS[2]
RSCCK / MRSCCK
RSCFS / MRSCFS
TSD[1] / MTSD[1]
TSD[2] / MTSD[2]
RSFS[3]
RSFS[4]
RSFS[5]
RSFS[6]
RSFS[7]
RSFS[8]
TSD[3]
TSD[4]
TSD[5]
TSD[6]
TSD[7]
TSD[8]
Name
Output
Type
Input
Input
Input
PQFP PBGA
120
109
105
103
101
119
115
113
111
95
90
87
82
79
76
71
68
99
Pin No.
G12
H12
D11
E11
L12
A11
A12
B11
J12
J10
D9
A5
B5
B7
D6
A8
D7
B9
RSFS[1:8]: Receive Side System Frame Pulse for Framer 1 ~ 8
In E1 mode, RSFSn can be configured to indicate the beginning of Basic Frame, or CRC Multi-Frame or/and Signal-
ing Multi-Frame for data stream on RSDn. When configured for the Basic Frame, RSFSn will pulse high/low during
the first bit of each Basic Frame. When configured for CRC Multi-Frame, RSFSn will pulse during the first bit of the
first frame of the CRC Multi-Frame. When configured for the Signaling Multi-Frame, RSFSn will pulse during the
first bit of the first frame of the Signaling Multi-Frame. When configured to indicate both Signaling and CRC Multi-
Frame, RSFSn will go high/low on the first bit of the first frame of the Signaling Multi-Frame and go the opposite
after the first bit of the first frame of the CRC Multi-Frame.
In T1/J1 mode, RSFSn can be configured to indicate each F-bit, or the first F-bit of every 12-frame SFs / every 24-
frame ESFs. RSFSn pulses during the above F-bit.
In both E1 and T1/J1 modes, when Receive Clock Master mode is active, RSFSn is updated on the active edge of
the corresponding RSCKn. When Receive Clock Slave mode is active, RSFSn is updated on the active edge of
RSCCK.
MRSFS[1:2]: Multiplexed Receive Side System Frame Pulse
When the multiplexed bus structure is configured, the signals on these pins indicate the beginning of a multiplexed
frame. MRSFS[1:2] are updated on the active edge of MRSCCK.
RSCCK: Receive Side System Common Clock
RSCCK is used only in Receive Clock Slave mode. In E1 mode, it is a 2.048 or 4.096 MHz clock. In T1 mode, it is a
1.544 or 2.048 or 4.096 MHz clock. In Receive Clock Slave RSCK Reference mode, RSDn and RSFSn are updated
and RSCFS is sampled on the active edge of RSCCK. In Receive Clock Slave External Signaling mode, RSDn,
RSFSn and RSSIGn are updated and RSCFS is sampled on the active edge of RSCCK.
MRSCCK: Multiplexed Receive Side System Common Clock
When the multiplexed bus structure is configured, MRSCCK is an 8.192 or 16.384 MHz clock for the receive system
multiplexed bus. MRSCFS is sampled and MRSD[1:2], MRSFS[1:2] and MRSSIG[1:2] are updated on the active
edge of MRSCCK.
RSCFS: Receive Side System Common Frame Pulse
In Receive Clock Slave mode, RSCFS can be selected as a frame alignment reference. It is asserted on the
request of each Basic Frame or each Multi-Frame in E1 mode, or it is asserted on the request of F-bit in T1/J1
mode. RSCFS is sampled on the active edge of RSCCK.
MRSCFS: Multiplexed Receive Side System Common Frame Pulse
When the multiplexed bus structure is configured, the signal on this pin aligns the multiplexed frame to the back-
plane timing. MRSCFS is sampled on the active edge of MRSCCK.
TSD[1:8]: Transmit Side System Data for Framer 1 ~ 8
The data streams from the system backplane are input on these pins.
In Transmit Clock Master mode, TSDn is sampled on the active edge of the corresponding LTCKn.
In Transmit Clock Slave mode, TSDn is sampled on the active edge of TSCCKB.
MTSD[1:2]: Multiplexed Transmit Side System Data
When the multiplexed bus structure is configured, the data stream from the backplane is carried on the multiplexed
bus for the selected framers. MTSD[1:2] are sampled on the active edge of MTSCCKB.
7
Description
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009