IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 260

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
Registers 04A-04FH, 0CA-0CFH, 14A-14FH, 1CA-1CFH, 24A-24FH, 2CA-2CFH, 34A-34FH, 3CA-3CFH:
second when the AUTOUPDATE (b0, T1/J1-000H) is set. The PMON Error Count registers for eight framers are updated by writing to the Chip ID/Glo-
bal PMON Update register (T1/J1-00CH).
T1 / J1 PMON BEE Count (LSB) (04AH, 0CAH, 14AH, 1CAH, 24AH, 2CAH, 34AH, 3CAH)
T1 / J1 PMON BEE Count (MSB) (04BH, 0CBH, 14BH, 1CBH, 24BH, 2CBH, 34BH, 3CBH)
calculated CRC-6
T1 / J1 PMON FER Count (LSB) (04CH, 0CCH, 14CH, 1CCH, 24CH, 2CCH, 34CH, 3CCH)
T1 / J1 PMON FER Count (MSB) (04DH, 0CDH, 14DH, 1CDH, 24DH, 2CDH, 34DH, 3CDH)
Programming Information
Bit Name
Bit Name
Bit Name
Bit Name
Default
Default
Bit No.
Default
Bit No.
Default
Bit No.
Bit No.
Type
Type
The PMON Error Count registers for a single framer are updated as a group by writing to any of the PMON count registers or updated every 1
When the chip is reset, the contents of the PMON Error Count registers are unknown until the first latching of performance data is performed.
Type
In the ESF format, the BEE[11:0] represent the number of the CRC-6 errors, that is, the differences between the received CRC-6 and the local
In the SF format, the BEE[11:0] represent the number of the bit errors in the Frame Alignment Pattern.
This register is updated on the defined intervals.
The FER[8:0] represent the number of the bit errors in the Frame Alignment Pattern.
This register is updated on the defined intervals.
Type
BEE7
FER7
R
X
R
X
7
7
7
7
BEE6
FER6
R
R
6
X
6
X
6
6
Reserved
BEE5
FER5
R
X
R
X
5
5
5
5
Reserved
BEE4
FER4
R
X
R
X
4
4
4
4
250
BEE11
BEE3
FER3
R
X
R
X
R
X
3
3
3
3
BEE10
BEE2
FER2
R
R
2
X
R
2
2
X
2
X
T1 / E1 / J1 OCTAL FRAMER
BEE9
BEE1
FER1
R
X
1
R
X
1
R
X
1
1
March 5, 2009
FER8
BEE8
BEE0
FER0
R
X
R
X
0
R
X
0
R
X
0
0