IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 104

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
4
4.1
4.1.1
default values.
(b0, E1-00AH / b0, T1/J1-00DH) in its framer is set. The device can also
be reset anytime when the RST pin is low for at least 100 ns.
Operation
Table 39: Default Setting in Receive Path in E1 Mode
Table 40: Default Setting in Transmit Path in E1 Mode
PRGD
Transmit System Interface
Frame Generator
HDLC Transmitter #1, #2, #3
Line Interface
Line Interface
Frame Processor
HDLC Receiver #1, #2, #3
Receive System Interface
PRGD
When the device is powered-up, all the registers contain their
Any of the eight framers can be reset anytime when the RESET
OPERATION
E1 MODE
DEFAULT SETTING
Function Block
Function Block
- The PRGD is configured to insert test patterns to Frame 1.
- In the Transmit Clock Slave External Signaling Mode.
- The data on the TSDn and TSSIGn pins is sampled on the rising edge of TSCCKB.
- CRC Multi-Frame is disabled.
- Channel Associated Signaling is enabled.
- THDLCs are disabled.
- LTDn outputs Non-Return to Zero (NRZ) data and is updated on the falling edge of LTCKn.
- TJAT Clock Divisors (N1, N2) are set to ‘2F’.
- Digital jitter attenuation is enabled. The PLL is synchronized to the TSCCKB clock. The smoothed clock output from
the PLL is selected as LTCKn.
- LRDn inputs Non-Return to Zero (NRZ) data and is sampled on the rising edge of LRCKn.
- The RJAT Clock Divisors (N1, N2) are set to ‘2F’.
- Basic Frame per G.704 with CRC Multi-Frame is enabled.
- Channel Associated Signaling is enabled.
- RHDLCs are disabled.
- In the Receive Clock Slave External Signaling Mode.
- The data on the RSDn, RSSIGn pins is updated on the rising edge of RSCCK.
- RSCFS indicates Basic Frame Alignment.
- The RSDn, RSSIGn, RSFSn pins are held in high-impedance state.
- The PRGD is configured to monitor the extracted data patterns in Frame 1.
94
ing settings:
the E1 mode is desired, the TEMODE (b0, 400H) must be set to logic 0.
is illustrated in Table 39.
path is illustrated in Table 40.
After the hardware reset, the IDT82V2108 will default to the follow-
- Mode: the default operation mode of the device is T1 mode. When
- Receive Path: the default setting of each block in the receive path
- Transmit Path: the default setting of each block in the transmit
Default Setting Description
Default Setting Description
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009