IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 40

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
3.11
received data to the system back-plane. The data from the eight framers
can be aligned with each other or be output independently. The timing
clocks and framing pulses can be provided by the system back-plane
common to eight framers, or obtained from the far end of the individual
eight framers. The Receive System Interface supports various configu-
rations to meet various requirements in different applications.
3.11.1
plexed Mode or Multiplexed Mode. In the Non-multiplexed Mode, the
RSDn pin is used to output the received data from each framer at a bit
rate of 2.048 Mb/s. While in the Multiplexed Mode, the received data
from the eight framers is byte-interleaved to form two high speed data
streams and outputs on the MRSD1 and MRSD2 pins at a bit rate of
8.192 Mb/s.
on RSDn pin is provided by the system side and shared by all eight
Table 10: E1 Mode Receive System Interface in Different Operation Modes
3.11.1.1
mon Clock (RSCCK) is provided by the system side. It is used as a com-
mon timing clock for all eight framers. The speed of RSCCK can be
chosen by the CMS (b2, E1-010H) to be the same as the received data
(2.048MHz), or double of the received data (4.096 MHz). The CMS (b2,
E1-010H) of the eight framers should be set to the same value. If the
Functional Description
Table 11: Operation Mode Selection in E1 Receive Path
Note:
* In the Receive Clock Slave mode and Receive Multiplexed mode, there are two framing signals. In the Receive Clock Slave mode, the framing pulses on RSCFS can be ignored for
some framers by setting the FPMODE (b5, E1-011H) to ‘0’. However, in the Receive Multiplexed mode, when the FPMODE (b5, E1-011H) of any of the eight framers is configured as logic
1, all the others are taken as logic 1. Only when all the FPMODE (b5, E1-011H) of the eight framers are configured as logic 0, the frame pulses on MRSCFS can be ignored. That is, the
FPMODE (b5, E1-011H) should be configured to the same value in the Receive Multiplexed mode.
1 1 (all the eight framers should be set)
Non-Multiplexed
The Receive System Interface determines how to output the
In E1 mode, the Receive System Interface can be set in Non-multi-
In the Non-multiplexed Mode, if the timing signal for clocking data
In the Receive Clock Slave Mode, the Receive Side System Com-
Mode
RECEIVE SYSTEM INTERFACE (RESI)
(b1~0, E1-010H)
E1 MODE
RATE[1:0]
Receive Clock Slave Mode
0 1
Clock Master
Clock Slave
Multiplexed Mode
Operation Mode
Mode
Mode
Fractional E1 (with F-bit)
External Signaling
RSCK Reference
Full E1
(b5, E1-010H)
RSCKSLV
1
0
1
Data Pin
MRSD
RSDn
RSDn
RSDn
RSDn
(b6, E1-001H)
RSSIG_EN
0
1
1
-
30
Clock Pin
MRSCCK
RSCCK
RSCCK
framers, the Receive System Interface should be set in Receive Clock
Slave mode. If the timing signal for clocking data on each RSDn pin is
received from each line side, the Receive System Interface should be
set in Receive Clock Master mode.
RSSIGn is used to output a reference clock, the Receive System Inter-
face is in Receive Clock Slave RSCK Reference Mode. If the RSCKn/
RSSIGn pin is used to output the extracted signaling bits, the Receive
System Interface is in Receive Clock Slave External Signaling mode.
an E1 basic frame is clocked out by RSCKn, the Receive System Inter-
face is in Receive Clock Master Full E1 mode. If the data in only some of
the time slots in an E1 frame is clocked out by RSCKn, the Receive Sys-
tem Interface is in Receive Clock Master Fractional E1 (with F-bit) Mode.
ation modes. To set the receive system interface of each framer into var-
ious operation modes, the registers must be configured as Table 11.
RSCKn
RSCKn
speed of RSCCK is double that of the received data stream, there will be
two active edges in one bit duration. In this case, the
RSD_RSCFS_EDGE (b5, E1-014H) determines the active edge to
update the signal on the RSDn, RSSIGn and RSFSn pins; however, the
pulse on RSCFS (if exists) is always samples on its first active edge.
mon Frame Pulse (RSCFS) is used as a common framing signal to align
(b7~6, E1-010H)
In the Receive Clock Slave mode, if the multi-function pin RSCKn/
In the Receive Clock Master mode, if the data in all 32 time slots in
Table 10 summarizes the receive system interface in different oper-
FRACTN[1:0]
In the Receive Clock Slave Mode, the Receive Side System Com-
0 0
1 0
1 1
-
-
-
MRSCFS & MRSFS *
RSCFS & RSFSn *
RSCFS & RSFSn *
Framing Pin
RSFSn
RSFSn
Receive Clock Master Fractional E1 with F-bit
Receive Clock Slave External Signaling
Receive Clock Slave RSCK Reference
Receive Clock Master Fractional E1
Receive Clock Master Full E1
Signaling Pin
Receive Multiplexed
MRSSIG
RSSIGn
T1 / E1 / J1 OCTAL FRAMER
Operation Mode
No
No
No
Reference Clock Pin
March 5, 2009
RSCKn
No
No
No
No