IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 149

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
E1 Data Link Micro Select / Framer Reset (00AH, 08AH, 10AH, 18AH, 20AH, 28AH, 30AH, 38AH)
RHDLCSEL[1:0]:
access one HDLC controller. These bits must be set before using the HDLC controller.
THDLCSEL[1:0]:
access one HDLC controller. These bits must be set before using the HDLC controller.
TXCISEL:
extracted bit in the received data stream and the inserted bit in the transmitting data stream respectively. So this bit is used to decide whether the
Read/Write operation on the registers addressed from E1-028H to E1-02DH is for HDLC receiver or for HDLC transmitter.
RESET:
a logic 0 must be written to bring the framer out of reset. Holding the framer in a reset state effectively puts it into a low power standby mode. A hard-
ware reset clears the RESET bit, the bits in this register and the V52DIS (b3, E1-007H).
Programming Information
Bit Name
Default
Bit No.
Type
The RHDLCSEL[1:0] select one of the three HDLC Receivers to be accessed by the microprocessor. At one time, the microprocessor can only
The THDLCSEL[1:0] select one of the three HDLC Transmitters to be accessed by the microprocessor. At one time, the microprocessor can only
The registers addressed from E1-028H to E1-02DH are shared by HDLC Receiver and HDLC Transmitter. They decide the position of the
= 0: The Read/Write operation on registers addressed from 028 H to 02D H is for HDLC receiver.
= 1: The Read/Write operation on registers addressed from 028H to 02D H is for HDLC transmitter.
This bit implements a software reset for individual framer.
= 0: normal operation.
= 1: The corresponding framer is held in reset. However, this bit, the bits in this register and the V52DIS (b3, E1-007H) will not be reset. Therefor,
RHDLCSEL[1]
R/W
X
7
RHDLCSEL[0]
R/W
6
X
THDLCSEL[1]
THDLCSEL[1:0]
R/W
RHDLCSEL[1:0]
X
5
00
01
10
11
00
01
10
11
THDLCSEL[0]
R/W
X
4
139
HDLC Transmitter
HDLC Receiver
RHDLC #1
RHDLC #2
RHDLC #3
Reserved
THDLC #1
THDLC #2
THDLC #3
Reserved
TXCISEL
R/W
X
3
2
Reserved
T1 / E1 / J1 OCTAL FRAMER
1
March 5, 2009
RESET
R/W
0
0