MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 89

IC MPU 32BIT 66MHZ 196-MAPBGA

MCF5272CVF66

Manufacturer Part Number
MCF5272CVF66
Description
IC MPU 32BIT 66MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5272CVF66

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Not Compliant

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Table 2-11
Table 2-12
MAC unit, along with other MOVE.L timings. Execution times for moving contents of the ACC or
MACSR into a destination location represent the best-case scenario when the store instruction is executed
and no load, MAC, or MSAC instructions are in the MAC execution pipeline. In general, these store
operations require only one cycle for execution, but if they are preceded immediately by a load, MAC, or
MSAC instruction, the MAC pipeline depth is exposed and execution time is three cycles.
Freescale Semiconductor
(d8,PC,Xi*SF)
(d8,Ay,Xi*SF)
Opcode
move.l
move.l
move.l
move.l
move.l
move.l
move.l
(d16,PC)
(d16,Ay)
Source
#<xxx>
(xxx).w
(xxx).l
(Ay)+
–(Ay)
(Ay)
Dy
Ay
lists timings for MOVE.L.
gives execution times for MOVE.L instructions accessing program-visible registers of the
<ea>,MACSR
MACSR,CCR
<ea>,MASK
MACSR,Rx
<ea>,ACC
MASK,Rx
ACC,Rx
<ea>
1(0/0)
1(0/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
1(0/0)
Rx
MCF5272 ColdFire
1(0/0)
2(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
Rn
1(0/1)
1(0/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(0/1)
(Ax)
Table 2-11. Move Long Execution Times
Table 2-12. Move Execution Times
(An)
®
Integrated Microprocessor User’s Manual, Rev. 3
(Ax)+
1(0/1)
1(0/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(0/1)
(An)+
–(An)
Destination
1(0/1)
1(0/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
3(1/1)
2(1/1)
2(1/1)
3(1/1)
2(0/1)
–(Ax)
2(1/1)
Effective Address
(d16,An)
(d16,Ax)
1(0/1)
1(0/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
2(1/1)
(d8,An,Xi*SF)
(d8,Ax,Xi*SF)
2(0/1)
2(0/1)
3(1/1)
3(1/1)
3(1/1)
(xxx).wl
ColdFire Core
(xxx).wl
1(0/1)
1(0/1)
2(1/1)
2(1/1)
2(1/1)
#<xxx>
1(0/0)
2(0/0)
1(0/0)
2-21

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