MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 216

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

DMA Controller
10.3.2
The DIR,
Table 10-3
10-4
15–13
Bits
Bits
1–0
7–5
12
11
10
9
8
Reset
Field
Addr
R/W
ASCEN Address sequence complete interrupt enable.
INVEN
Name
SRCS
Name
TCEN
TEEN
Figure
—
—
—
describes DIR fields.
15
DMA Interrupt Register (DIR)
—
Source data transfer type. Determines the amount of data the DMA controller fetches and buffers data from
the source address. When there are enough bytes to perform a destination data write of the size
programmed in DSTS, the data is written to the destination address. Thus source accesses can be
longword type and destination addresses can be line burst type. In this case, 4 longword reads are
performed followed by an indivisible burst write of 4 longwords.
The most efficient data transfer method is to use longword or line burst transfer types.
10-2, contains status bits and their corresponding interrupt enables.
Reserved, should be cleared.
Invalid combination interrupt enable.
0 INV interrupt is disabled.
1 INV interrupt is enabled.
0 ASC interrupt is disabled.
1 ASC interrupt is enabled.
Reserved, should be cleared.
Transfer error interrupt enable.
0 TE interrupt is disabled.
1 TE interrupt is enabled.
Transfer complete interrupt enable.
0 TC interrupt is disabled.
1 TC interrupt is enabled.
Reserved, should be cleared.
MCF5272 ColdFire
13
INVEN ASCEN
SRCS
12
00
01
10
11
Table 10-2. DMR Field Descriptions (continued)
Figure 10-2. DMA Interrupt Register (DIR)
11
Table 10-3. DIR Field Descriptions
Longword
Byte
Word
16-byte line burst
®
Data Transfer Type
Integrated Microprocessor User’s Manual, Rev. 3
—
10
0000_0000_0000_0000
TEEN TCEN
9
MBAR + 0x00E6
R/W
8
Description
Description
4
1
2
16. Valid only for SDRAM.
7
—
Address Incremented by
5
INV
4
ASC
3
Freescale Semiconductor
—
2
TE
1
TC
0