MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 230
![IC MPU 32BIT 66MHZ 196-MAPBGA](/photos/13/94/139406/mcf5272cvf66_sml.jpg)
MCF5272CVF66
Manufacturer Part Number
MCF5272CVF66
Description
IC MPU 32BIT 66MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Not Compliant
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Ethernet Module
11.5.2
An event that sets a bit in EIR generates an interrupt if the corresponding bit in the interrupt mask register
(EIMR) is set. Bits in the interrupt event register are cleared when a one is written to them. Writing a zero
has no effect.
11-12
20–0
Bits
31
30
29
28
27
26
25
24
23
22
21
Reset
Reset
Field HBERR BABR BABT GRA
Field
Addr
R/W
R/W
HBERR
EBERR
UMINT
Name
BABR
Interrupt Event Register (EIR)
BABT
GRA
RXF
RXB
TXF
TXB
MII
31
15
—
Heartbeat error. A heartbeat was not detected within the heartbeat window following a transmission.
Babbling transmit error. The transmitted frame length has exceeded MAX_FL bytes. This condition is
usually caused by a frame that is too long being placed into the transmit data buffer(s). Truncation does
not occur.
Graceful stop complete. A graceful stop, which was initiated by setting X_CTRL[GTS], is now complete.
This bit is set as soon as the transmitter has finished transmitting any frame that was in progress when
GTS was set.
Transmit frame interrupt. A frame has been transmitted and that the last corresponding buffer descriptor
has been updated.
Receive frame interrupt. A frame has been received and the last corresponding buffer descriptor has
been updated.
Receive buffer interrupt. A receive buffer descriptor has been updated.
not maskable.
Babbling receive error. A frame was received with length in excess of MAX_FL bytes.
Transmit buffer interrupt. A transmit buffer descriptor has been updated.
MII interrupt. The MII has completed the data transfer requested.
FEC bus error. A bus error occurred when the FEC was accessing an internal bus.
Unmasked interrupt status. An interrupt is currently being asserted to the interrupt controller. This bit is
Reserved, should be cleared.
30
MCF5272 ColdFire
29
Figure 11-6. Interrupt Event Register (EIR)
28
Table 11-8. EIR Field Descriptions
TXF
®
27
Integrated Microprocessor User’s Manual, Rev. 3
TXB
26
0000_0000_0000_0000
0000_0000_0000_0000
MBAR + 0x844
RXF
Read/write
Read/write
25
—
RXB
Description
24
MII EBERR UMINT
23
22
21
20
Freescale Semiconductor
—
16
0
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