MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 110
![IC MPU 32BIT 66MHZ 196-MAPBGA](/photos/13/94/139406/mcf5272cvf66_sml.jpg)
MCF5272CVF66
Manufacturer Part Number
MCF5272CVF66
Description
IC MPU 32BIT 66MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Not Compliant
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Manufacturer
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Part Number:
MCF5272CVF66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5272CVF66
Manufacturer:
FREESCALE
Quantity:
20 000
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Part Number:
MCF5272CVF66 K75N
Manufacturer:
ST
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Part Number:
MCF5272CVF66J
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Local Memory
4.5.2
The instruction cache is physically connected to the ColdFire core's local bus, allowing it to service all
instruction fetches from the ColdFire core and certain memory fetches initiated by the debug module.
Typically, the debug module's memory references appear as supervisor data accesses but the unit can be
programmed to generate user-mode accesses and/or instruction fetches. The instruction cache processes
any instruction fetch access in the normal manner.
4.5.2.1
Because both the instruction cache and high-speed SRAM module are connected to the ColdFire core's
local data bus, certain user-defined configurations can result in simultaneous instruction fetch processing.
If the referenced address is mapped into the SRAM module, that module services the request in a single
cycle. In this case, data accessed from the instruction cache is discarded without generating external
memory references. If the address is not mapped into SRAM space, the instruction cache handles the
request in the normal fashion.
4.5.2.2
The instruction cache does not monitor ColdFire core data references for accesses to cached instructions.
Therefore, software must maintain cache coherency by invalidating the appropriate cache entries after
modifying code segments.
4-8
31
Instruction Cache Operation
Local Address Bus
Interaction with Other Modules
Cache Coherency and Invalidation
MCF5272 ColdFire
9
43
Figure 4-3. Instruction Cache Block Diagram
1 2
0
Fill Hit
=
®
Integrated Microprocessor User’s Manual, Rev. 3
31
Line
31
Tag Hit
Tag
=
Address
9
Buffer
0
31
4
Line Buffer Data Storage
External Data[31:0]
31
MUX
Local Data Bus
Data
MUX
Freescale Semiconductor
0
0
63
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