MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 537

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Reset
ROM
ROMBAR
Freescale Semiconductor
TMR,
transmit
trigger definition,
TRR,
UACR,
UART modules,
UCR,
UCSR,
UDU/UDL, 16-14, 16-14, 16-15,
UIP,
UIPCR,
UISR,
USB
USB general,
VB,
vector base, 2-8,
WAREG/WDREG,
watchdog
WCR,
WCREG,
WDMREG,
WER,
WIRR,
write control,
write debug module,
instruction cache,
base address register,
operation,
overview,
programming model,
overview,
power management programming,
mode,
reference,
control,
descriptor active,
FIFO watermark,
access,
alternate settings,
endpoint
frame number,
function address,
counter,
event,
interrupt reference,
control,
data,
data present,
interrupt mask,
status interrupt,
2-8
16-17
15-4
16-9
15-3
6-13
16-12
6-13
16-8
6-12
16-12
16-11
6-13
15-3
12-30
12-27
5-31
11-25
4-5
4-5
4-5
6-13
5-33
15-4
12-17–12-20
12-9–12-28
5-31
2-8
16-2–16-18
12-9
12-28
5-14
4-10
12-11
11-16
11-21
12-12
5-23
12-26
12-25
5-33
4-5
6-12
4-5
MCF5272 ColdFire
16-16
4-6
®
Integrated Microprocessor User’s Manual, Rev. 3
S
SDCR,
SDRAM
Serial management channel timing,
Signals
SIM
Software watchdog timer,
SRAM
auto initialization,
banks, page hits, page misses,
configuration register,
controller signals,
devices interface,
interface,
performance,
power-down and self-refresh,
read accesses,
refresh timing,
registers,
solving timing issues,
timing register,
write accesses,
bus control,
bypass,
chip selects,
clear-to-send,
CPU clock and reset,
CPU external clock,
DRESETEN,
Ethernet module,
Hi-Z,
output enable/read,
PWM module,
read/write,
receive serial data input,
request to send,
reset output,
timer module, 19-27,
transfer acknowledge,
transmit serial data output,
USB
overview,
programming model,
register memory map,
receive data negative,
receive serial data input,
Rx data output,
suspend driver,
transmit data negative,
transmit serial data output,
transmitter output enable,
USB_CLK,
USB_D+ and USB_D-,
wake-on-ring,
9-12
19-22
19-22
9-6
9-14
1-5
19-21
19-20–19-23
19-19
19-23
9-10
19-23
19-25
9-15
19-26
9-20
19-29
9-18
9-8
19-25
19-26
19-27–19-29
9-4
19-26
19-26
9-1
9-9
19-20
19-23
19-23
19-27
6-2
9-12
19-22
6-2
9-6
6-11
19-25
19-25
19-26
19-26
19-24
19-25
19-26
19-25
9-9
9-6
23-20
Index-7
Index