MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 310

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Physical Layer Interface Controller (PLIC)
13-14
0x0394
0x0398
0x039C
0x035C
0x036C
0x037C
0x038C
0x0340
0x0344
0x0348
0x0350
0x0354
0x0358
0x0360
0x0364
0x0368
0x0370
0x0374
0x0378
0x0383
0x0384
0x0388
0x0390
MBAR
Offset
Port0 GCI C/I Rx (P0GCIR) Port1 GCI C/I Rx (P1GCIR) Port2 GCI C/I Rx (P2GCIR) Port3 GCI C/I Rx (P3GCIR)
Port0 GCI C/I Tx (P0GCIT) Port1 GCI C/I Tx (P1GCIT) Port2 GCI C/I Tx (P2GCIT) Port3 GCI C/I Tx (P3GCIT)
Port0 D Data Transmit
Port0 Interrupt Configuration register (P0ICR)
Port2 Interrupt Configuration register (P2ICR)
Port0 GCI/IDL Configuration register (P0CR)
Port2 GCI/IDL Configuration register (P2CR)
Aperiodic Interrupt status register (PASR)
Reserved
(P0DTR)
[31:24]
Port0 GCI monitor Rx (P0GMR)
Port2 GCI monitor Rx (P2GMR)
Port0 GCI monitor Tx (P0GMT)
Port2 GCI monitor Tx (P2GMT)
Port0 periodic status (P0PSR)
Port2 periodic status (P2PSR)
MCF5272 ColdFire
Port0 Sync Delay (P0SDR)
Port2 Sync Delay (P2SDR)
Table 13-1. PLIC Module Memory Map (continued)
Reserved
Reserved
Port1 D Data Transmit
GCI monitor Tx status
®
Integrated Microprocessor User’s Manual, Rev. 3
Reserved
Reserved
(PGMTS)
(P1DTR)
[23:16]
Port2 B2 Data Transmit (P2B2TR)
Port3 B2 Data Transmit (P3B2TR)
Port2 D Data Transmit
GCI monitor Tx abort
Port1 Interrupt Configuration register (P1ICR)
Port3 Interrupt Configuration register (P3ICR)
Port1 GCI/IDL Configuration register (P1CR)
Port3 GCI/IDL Configuration register (P3CR)
Reserved
(PGMTA)
(P2DTR)
[15:8]
Port1 GCI monitor Rx (P1GMR)
Port3 GCI monitor Rx (P3GMR)
Port1 GCI monitor Tx (P1GMT)
Port3 GCI monitor Tx (P3GMT)
Port1 periodic status (P1PSR)
Port3 periodic status (P3PSR)
D-Channel Request (PDRQR)
Port1 Sync Delay (P1SDR)
Port3 Sync Delay (P3SDR)
Clock Select (PCSR)
Loop back Control (PLCR)
GCI C/I D-Channel Status
Port3 D Data Transmit
Freescale Semiconductor
GCI C/I Tx Status
(PGCITSR)
Reserved
(PDCSR)
(P3DTR)
[7:0]