MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 138
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MCF5272CVF66
Manufacturer Part Number
MCF5272CVF66
Description
IC MPU 32BIT 66MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Not Compliant
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Debug Support
5.5.3.1
All ColdFire Family BDM commands include a 16-bit operation word followed by an optional set of one
or more extension words, as shown in
Table 5-18
5.5.3.1.1
Some commands require extension words for addresses and/or immediate data. Addresses require two
extension words because only absolute long addressing is permitted. Longword accesses are forcibly
longword-aligned and word accesses are forcibly word-aligned. Immediate data can be 1 or 2 words long.
Byte and word data each requires a single extension word and longword data requires two extension words.
Operands and addresses are transferred most-significant word first. In the following descriptions of the
BDM command set, the optional set of extension words is defined as address, data, or operand data.
5-20
15–10
7–6
5–4
2–0
Bit
9
8
3
15
Operation Specifies the command. These values are listed in
Operand
Register
Name
R/W
Size
describes BDM fields.
A/D
00
0
ColdFire BDM Command Format
Extension Words as Required
Operation
Reserved
Direction of operand transfer.
0 Data is written to the CPU or to memory from the development system.
1 The transfer is from the CPU to the development system.
Operand data size for sized operations. Addresses are expressed as 32-bit absolute values. Note that a
command performing a byte-sized memory read leaves the upper 8 bits of the response data undefined.
Referenced data is returned in the lower 8 bits of the response.
00 Byte8 bits
01 Word16 bits
10 Longword32 bits
11 Reserved—
Reserved
Address/data. Determines whether the register field specifies a data or address register.
0 Indicates a data register.
1 Indicates an address register.
Contains the register number in commands that operate on processor registers.
Operand SizeBit Values
MCF5272 ColdFire
Figure 5-15. BDM Command Format
Table 5-18. BDM Field Descriptions
10
®
Figure
Integrated Microprocessor User’s Manual, Rev. 3
0
9
Extension Word(s)
5-15.
R/W
8
7
Op Size
Description
6
Table
5-17.
0
5
0
4
A/D
3
Freescale Semiconductor
2
Register
0
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