MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 314
![IC MPU 32BIT 66MHZ 196-MAPBGA](/photos/13/94/139406/mcf5272cvf66_sml.jpg)
MCF5272CVF66
Manufacturer Part Number
MCF5272CVF66
Description
IC MPU 32BIT 66MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Not Compliant
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MCF5272CVF66
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Physical Layer Interface Controller (PLIC)
13.5.6
All bits in these registers are read/write and are set on hardware or software reset.
The PLTD registers contain four frames of D-channel transmit data, packed from lsb to msb, for each of
the four physical ports on the MCF5272. P0DTR is the D-channel byte for port 0, P1DTR the D channel
for port 1, and so on.
The four byte-addressable 8-bit registers, P0DTR–P3DTR, are packed to form one 32-bit register, PLTD.
PLTD is aligned on a long-word boundary at MBAR + 0x348 and can be read as a single 32-bit register.
P0DTR is located in the MSB of the PLTD register, P3DTR is located in the LSB of the PLTD register.
13.5.7
PnCR are registers containing configuration information for each of the four ports on the MCF5272.
All bits in these registers are read/write and are cleared on hardware or software reset.
13-18
Reset
Reset
P0CR ON/OFF
P1CR ON/OFF
P2CR ON/OFF
P3CR ON/OFF
Reset
Field
Field
Addr
R/W
Addr
R/W
R/W
D Data Transmit Registers (P0DTR–P3DTR)
31
15
Port Configuration Registers (P0CR–P3CR)
15
—
—
—
14
MCF5272 ColdFire
MBAR + 0x348 (P0DTR); 0x349 (P1DTR); 0x34A (P2DTR); 0x34B (P3DTR)
Figure 13-19. Port Configuration Registers (P0CR–P3CR)
Figure 13-18. D Transmit Data Registers P0DTR–P3DTR
—
—
M
MBAR + 0x350 (P0CR); 0x352 (P1CR); 0x354 (P2CR); 0x356 (P3CR)
1111_1111
1111_1111
M
P0DTR
P2DTR
—
—
12
M/S G/S FSM ACT
—
—
—
11
®
Integrated Microprocessor User’s Manual, Rev. 3
G/S
—
—
10
0000_0000_0000_0000
—
—
—
9
Read/Write
Read/Write
Read/Write
24
ACT
8
—
—
8
DMX —
23
7
—
—
—
7
—
—
—
6
—
—
—
—
5
— SHB2 SHB1 ENB2 ENB1
— SHB2 SHB1 ENB2 ENB1
— SHB2 SHB1 ENB2 ENB1
— SHB2 SHB1 ENB2 ENB1
4
1111_1111
1111_1111
P1DTR
P3DTR
3
Freescale Semiconductor
2
1
0
16
0
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