MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 376

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

UART Modules
16.3.14 UART Receiver FIFO Registers (URFn)
The URFn registers contain control and status bits for the receiver FIFO. Note that some bits are read only.
Table 16-11
16-16
Bits
7–6
4–0
5
Address
Reset
Field
Name
R/W
FULL
RXS
RXB
describes URFn fields.
Receiver status. When written to, these bits control the meaning of UISRn[RxFIFO].
00 Inhibit receiver FIFO status indication in UISRn.
01 Receiver FIFO Š 25% full
10 Receiver FIFO Š 50% full
11 Receiver FIFO Š 75% full
When read, these bits indicate the emptiness level of the FIFO.
00 Receiver FIFO < 25% full
01 Receiver FIFO Š 25% full
10 Receiver FIFO Š 50% full
11 Receiver FIFO Š 75% full
Receiver FIFO full.
0 Receiver FIFO is not full and can be loaded with a character.
1 Receiver FIFO is full. Characters loaded from the receiver when the FIFO is full are lost.
This bit is identical to USRn[FFULL].
Receiver buffer data level. Indicates the number of bytes, between 0 and 24, stored in the receiver FIFO.
7
RXS
R/W
MCF5272 ColdFire
Figure 16-17. UART Receiver FIFO Registers (URFn)
6
Table 16-11. URFn Field Descriptions
FULL
R
®
5
Integrated Microprocessor User’s Manual, Rev. 3
MBAR + 0x12C (URF0), 0x16C (URF1)
4
0000_0000
Description
RXB
R
Freescale Semiconductor
0