MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 284
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MCF5272CVF66
Manufacturer Part Number
MCF5272CVF66
Description
IC MPU 32BIT 66MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Not Compliant
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Manufacturer
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Price
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MCF5272CVF66
Manufacturer:
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Quantity:
10 000
Part Number:
MCF5272CVF66
Manufacturer:
FREESCALE
Quantity:
20 000
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Part Number:
MCF5272CVF66 K75N
Manufacturer:
ST
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Part Number:
MCF5272CVF66J
Manufacturer:
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Quantity:
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Universal Serial Bus (USB)
12.3.2.17 USB Endpoint 1–7 Interrupt Mask Registers (EPnIMR)
Figure 12-20
Table 12-16
12-26
15–5
Bits
4–0
Bits
1
0
Reset
Field
Addr
R/W
Name
—
FIFO_LVL
lists field descriptions for the USB endpoint 1–7 interrupt mask register.
shows the USB endpoint 1–7 interrupt mask register.
Name
15
HALT
Reserved, should be cleared.
Interrupt mask. These bits are set when the user wants to activate the interrupt source for the specific bit.
Refer to
1 Interrupt Enabled
0 Interrupt Disabled
Figure 12-20. USB Endpoint 1-7 Interrupt Mask Registers (EP
MCF5272 ColdFire
Endpoint halt interrupt. Set when the endpoint n HALT_ST bit is set.
0 No interrupt pending
1 Endpoint n halted
FIFO threshold level reached interrupt. Indicates that the FIFO level has risen above or fallen below
the level set in the EPCTLn register for OUT or IN endpoints, respectively.
0 No interrupt pending
1 FIFO threshold level reached
Table 12-15
Table 12-15. EPnISR Field Descriptions (continued)
MBAR + 0x1092, 0x1096, 0x109A, 0x109E, 0x10A2, 0x10A6, 0x10AA
—
Table 12-16. EP
for a description of each interrupt source.
®
Integrated Microprocessor User’s Manual, Rev. 3
5
0000_0000_0000_0000
n
EOT_EN EOP_EN UNHALT_EN HALT_EN FIFO_LVL_EN
IMR Field Descriptions
4
R/W
Description
Description
3
2
n
IMR)
1
Freescale Semiconductor
0
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