MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 367
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MCF5272CVF66
Manufacturer Part Number
MCF5272CVF66
Description
IC MPU 32BIT 66MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5272CVF66
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Not Compliant
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16.3.3
The USRn,
Table 16-4
Freescale Semiconductor
Bits
7
6
5
4
3
2
Address
Reset
Field
TxEMP Transmitter empty.
R/W
TxRDY
Name
RB
OE
FE
PE
describes USRn fields.
Figure
UART Status Registers (USRn)
Received break. The received break circuit detects breaks that originate in the middle of a received
character. However, a break in the middle of a character must persist until the end of the next detected
character time.
0 No break was received.
1 An all-zero character of the programmed length was received without a stop bit. RB is valid only when
Framing error.
0 No framing error occurred.
1 No stop bit was detected when the corresponding data character in the FIFO was received. The stop-bit
Parity error. Valid only if RxRDY = 1.
0 No parity error occurred.
1 If UMR1n[PM] = 0x (with parity or force parity), the corresponding character in the FIFO was received with
Overrun error. Indicates whether an overrun occurs.
0 No overrun occurred.
1 One or more characters in the received data stream have been lost. OE is set upon receipt of a new
0 The transmitter buffer is not empty. Either a character is being shifted out, or the transmitter is disabled.
1 The transmitter has underrun (both the transmitter holding register and transmitter shift registers are
Transmitter ready.
0 The CPU loaded the transmitter holding register or the transmitter is disabled.
1 The transmitter holding register is empty and ready for a character. TxRDY is set when a character is sent
RB
7
RxRDY = 1. Only a single FIFO position is occupied when a break is received. Further entries to the FIFO
are inhibited until RxD returns to the high state for at least one-half bit time, which is equal to two
successive edges of the UART clock.
check occurs in the middle of the first stop-bit position. FE is valid only when RxRDY = 1.
incorrect parity. If UMR1n[PM] = 11 (multidrop), PE stores the received A/D bit.
character when the FIFO is full and a character is already in the shift register waiting for an empty FIFO
position. When this occurs, the character in the receiver shift register and its break detect, framing error
status, and parity error, if any, are lost. OE is cleared by the
The transmitter is enabled/disabled by programming UCRn[TC].
empty). This bit is set after transmission of the last stop bit of a character if there are no characters in the
transmitter holding register awaiting transmission.
to the transmitter shift register and when the transmitter is first enabled. If the transmitter is disabled,
characters loaded into the transmitter holding register are not sent.
16-4, shows status of the transmitter, the receiver, and the FIFO.
MCF5272 ColdFire
FE
6
Figure 16-4. UART Status Registers (USRn)
Table 16-4. USRn Field Descriptions
®
PE
5
Integrated Microprocessor User’s Manual, Rev. 3
MBAR + 0x104 (USR0), 0x144 (USR1)
OE
4
0000_0000
Read only
Description
TxEMP
3
RESET ERROR STATUS
TxRDY
2
FFULL
1
command in UCRn.
RxRDY
UART Modules
0
16-7
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