MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 277

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
Bits
5–4
3–2
7
6
1
0
CRC_ERR
OUT_LVL
IN_DONE
IN_LVL
Name
—
—
MCF5272 ColdFire
CRC error generation enable. This bit enables CRC error generation for debug and test purpose.
In order to use this feature, the DEBUG bit must be set. Enabling this bit causes a CRC error on
the next data packet transmitted. The CRC_ERR bit must be set again in order to generate
another CRC error. This bit only applies to IN transfers. This command bit is write-only and always
returns 0 when read.
1 CRC error generation if DEBUG = 1
0 default value
Reserved, should be cleared.
Endpoint 0 OUT FIFO level for interrupt. This field selects the FIFO level to generate an OUT_LVL
interrupt. The OUT_LVL interrupt is generated when the FIFO fills above the selected level.
00 FIFO 25% Full
01 FIFO
10 FIFO
11 FIFO 100% Full
Endpoint 0 IN FIFO level for interrupt. This field selects the FIFO level to generate an IN_LVL
interrupt. The IN_LVL interrupt is generated when the FIFO falls below the selected level.
00 FIFO 25% Empty
01 FIFO
10 FIFO
11 FIFO 100% Empty
This bit controls the USB's response to IN tokens from the host. This bit is set at Reset and must
be cleared by software when the last byte of a transfer has been written to the IN-FIFO. This bit is
then subsequently set by the USB core when an end of transfer (EOT) event occurs indicating that
the transfer has been completed. An end of transfer (EOT) event is indicated by one of the
following:
a) An IN packet is transmitted that contains less than the maximum number of bytes defined at
b) A zero length IN packet is transmitted. This occurs when the previously transmitted IN packet
0 CPU has completed writing to the IN-FIFO and transfer is in progress. The USB module will
1 Transfer completed or CPU Busy writing transfer into the IN-FIFO. The USB module will only
Reserved, should be cleared.
send any amount of data in the FIFO or a zero-length packet when the FIFO is empty.
send maximum size packets or NAK responses if the FIFO contains less than a maximum size
packet. This bit is set at Reset and on an EOT event.
Table 12-12. EP0CTL Field Descriptions (continued)
endpoint configuration.
was full, and no more data remains in the IN-FIFO. Hence a single zero length packet must be
sent to indicate EOT.
50%
75%
50%
75%
Full
Empty
Full
Empty
®
Integrated Microprocessor User’s Manual, Rev. 3
Description
Universal Serial Bus (USB)
12-19