MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 317

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
14–12
Bits
7–6
15
11
10
9
8
5
4
3
2
1
0
B2RIE
B1RIE
Name
B2TIE
B1TIE
GMR
DTIE
DRIE
GCR
GMT
GCT
—
—
IE
Interrupt enable. Allows the port to generate interrupts to the CPU. When cleared, the IE bit masks all
periodic and aperiodic interrupts associated with the respective port.
Reserved, should be cleared.
Interrupt enable for the C/I channel receive.
0 Interrupt masked
1 Interrupt enabled. When set, an interrupt is enabled which occurs when the corresponding GCR
C/I channel transmit Interrupt enable.
0 Interrupt masked
1 Interrupt enabled.
Interrupt enable for the monitor channel receive.
0 Interrupt masked
1 Interrupt enabled.
Interrupt enable for the monitor channel transmit.
0 Interrupt masked
1 Interrupt enabled.
Reserved, should be cleared.
D transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled.Interrupt occurs when the corresponding PnPSR[DTDE] or PnPSR[DTUE] is set.
B2 transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B2TDE] or PnPSR[B2TUE] is
B1 transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B1TDE] or PnPSR[B1TUE] is
D receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[DRDF] or PnPSR[DROE] is
B2 receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B2RDF] or PnPSR[B2ROE] is
B1 receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled.Interrupt occurs when the corresponding PnPSR[B1RDF] or PnPSR[B1ROE] is
MCF5272 ColdFire
status bit is set.
set.
set.
set.
set.
set.
Table 13-4. P0ICR–P3ICR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
Description
Physical Layer Interface Controller (PLIC)
13-21