HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 98

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 CPU
2.2.3
Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed
from any address, but an address error will occur if the word data starting from an address other
than 2n or longword data starting from an address other than 4n is accessed. In such cases, the data
accessed cannot be guaranteed (figure 2.11).
As the data format, either big endian or little endian byte order can be selected, according to the
MD5 pin at reset. When MD5 is low at reset, the processor operates in big endian. When MD5 is
high at reset, the processor operates in little endian.
2.3
The CPU core instructions are RISC-type instructions with the following features:
Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code
efficiency.
One Instruction per State: Pipelining is used, and basic instructions can be executed in one state.
At 160-MHz operation, one state is 6.25 ns.
Data Size: The basic data size for operations is longword. Byte, word, or longword can be
selected as the memory access size. Memory byte or word data is sign-extended and operated on
as longword data. Immediate data is sign-extended to longword size for arithmetic operations or
zero-extended to longword size for logical operations.
Rev.6.00 Mar. 27, 2009 Page 40 of 1036
REJ09B0254-0600
Address A + 4
Address A + 8
Address A
Data Format in Memory
Features of CPU Core Instructions
Address A
31
Byte 0
Word 0
Address A + 1
Figure 2.11 Byte, Word, and Longword Alignment
Big-endian mode
23
Byte 1
Longword
Address A + 2
15
Byte 2
Word 1
Address A + 3
7
Byte 3
0
Address A + 11
31
Byte 3
Word 1
Address A + 10
Little-endian mode
23
Byte 2
Longword
Address A + 9
15
Byte 1
Word 0
Address A + 8
7
Byte 0
0
Address A + 8
Address A + 4
Address A