HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 765
![IC SUPERH MPU ROMLESS 240BGA](/photos/28/61/286131/240-lfbga__plbg0240ja-a_sml.jpg)
HD6417727BP100BV
Manufacturer Part Number
HD6417727BP100BV
Description
IC SUPERH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP100BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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(1) Setup Stage
Notes: 1. The application analyzes command data from the host that must be processed by the application in
(USBIFR0/SETUP TS = 1)
Receive 8-byte command
SETUP token reception
2. When the transfer direction is control-out, enable an EP0i transfer request interrupt that is required
Set receive-end flag
of setup command
be processed by
the setup stage, and decides the following processing methods (for instance, data stage direction).
in the status stage. When the transfer direction is control-in, disable the interrupt since it is not
used.
To data stage
Command to
data in EP0s
application?
USB function
Yes
Figure 23.5 Setup Stage Operation
No
Interrupt request
processing by
this module
Automatic
Rev.6.00 Mar. 27, 2009 Page 707 of 1036
Clear EP0o FIFO (USBFCLR/EP0oCLR = 1)
Clear EP0i FIFO (USBFCLR/EP0iCLR = 1)
To control-in
data stage
Section 23 USB Function Controller
Decide data stage direction
Read 8-byte data from EP0s
Write 1 to EP0s read-end bit
(USBTRG/EP0s RDFN = 1)
(USBIFR0/SETUP TS = 0)
Decode command data
Clear SETUP TS flag
Application
*2
REJ09B0254-0600
To control-out
data stage
*1
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