HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 676

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 20 Serial IO (SIOF)
Bit 0—Receiving Operation Reset (RXRST): Setting to this bit becomes effective immediately.
After the setting 1 to this bit becomes effective, SIOF initializes the following registers and stop
receiving from RxD_SIO.
1. SIRDR register
2. Receiving FIFO write pointer and read pointer
3. RCRDY, RFFUL, and RDREQ bits of SISTR register
4. RXE bit
SIOF is cleared automatically when this bit completes the reset, so 0 is always read from this bit.
Bit 0: RXRST
0
1
20.2.7
This register set trigger point and show current available area of Transmit and Receive FIFO. This
register is initialized at power on reset or software reset.
Rev.6.00 Mar. 27, 2009 Page 618 of 1036
REJ09B0254-0600
Initial value:
Initial value:
R/W:
R/W:
FIFO Control Register (SIFCTR)
Bit:
Bit:
RFWM2 RFWM1 RFWM0
TFWM2
R/W
R/W
15
0
7
0
Description
Receiving operation is not reset
Receiving operation is reset
TFWM1
R/W
R/W
14
0
6
0
TFWM0
R/W
R/W
13
0
5
0
RFUA4
TFUA4
12
R
R
1
4
0
TFUA3
RFUA3
11
R
R
0
3
0
RFUA2
TFUA2
10
R
R
0
2
0
RFUA1
TFUA1
R
R
9
0
1
0
(Initial value)
RFUA0
TFUA0
R
R
8
0
0
0