HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 620
HD6417727BP100BV
Manufacturer Part Number
HD6417727BP100BV
Description
IC SUPERH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP100BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Section 18 Smart Card Interface
The receive margin is found from the following equation:
For smart card mode:
Where: M = Receive margin (%)
Using this equation, the receive margin when F = 0 and D = 0.5 is as follows:
Rev.6.00 Mar. 27, 2009 Page 562 of 1036
REJ09B0254-0600
data (RxD0)
Base clock
Synchro-
sampling
sampling
Receive
nization
M = (0.5 −
N = Ratio of bit rate to clock (N = 372)
D = Clock duty (D = 0 to 1.0)
L = Frame length (L = 10)
F = Absolute value of clock frequency deviation
M = (0.5 – 1/2 × 372) × 100% = 49.866%
timing
timing
Data
Figure 18.8 Receive Data Sampling Timing in Smart Card Mode
0
186 clock cycles
2N
1
) −
372 clock cycles
(L − 0.5)F −
Start
bit
185
D − 0.5
N
371 0
(1 + F) × 100%
D0
185
371 0
D1
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