HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 647

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

19.3
19.3.1
For serial communication, the SCIF has an asynchronous mode in which characters are
synchronized individually. Refer to section 17.3.2, Operation in Asynchronous Mode. The SCIF
has the 16-byte FIFO buffer for both transmit and receive, reduces an overhead of the CPU, and
enables continuous high-speed communication. Moreover, it has the RTS2 and CTS2 signals as
the modem control signals. The transmission format is selected in the serial mode register 2
(SCSMR2), as listed in table 19.6. The clock source of SCIF is determined by the combination of
CKE1 and CKE0 bits in the serial control register 2 (SCSCR2) as shown in table 19.7.
• Data length is selectable from seven or eight bits.
• Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The
• In receiving, it is possible to detect framing errors (FER), parity errors (PER), receive FIFO
• In transmitting, it is possible to detect transmit FIFO data empty.
• The number of stored data for both the transmit and receive FIFO registers is displayed.
• SCIF clock source
Table 19.6 SCSMR2 Settings and SCIF Transmit/Receive
Mode
Asynchronous
combination of the preceding selections constitutes the communication format and character
length.
data full, receive data ready, and breaks.
⎯ The SCIF operates using the on-chip baud rate generator, and can output a serial clock
signal with a frequency 16 times the bit rate.
Operation
Overview
SCSMR2 Settings
Bit 6
CHR
0
1
Bit 5
PE
0
1
0
1
Section 19 Serial Communication Interface with FIFO (SCIF)
Bit 3
STOP
0
1
0
1
0
1
0
1
Data
Length
8-bit
7-bit
Rev.6.00 Mar. 27, 2009 Page 589 of 1036
SCIF Transmit/Receive
Parity
Bit
Not set
Set
Not set
Set
Stop Bit Length
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
1 bit
2 bits
REJ09B0254-0600