HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 674
HD6417727BP100BV
Manufacturer Part Number
HD6417727BP100BV
Description
IC SUPERH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP100BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Section 20 Serial IO (SIOF)
20.2.6
This register sets the operating states of SIOF.
This register is initialized at power on reset or software reset.
Bits 13 to 10, and 7 to 2—Reserved
Bit 15—Serial Clock Output Enable (SCKE): This bit is effective in master mode. When 1 is
set to this bit, SIOF initializes baud rata generator, then starts, operation, and outputs the clock that
is generated by baud rate generator to SCK_SIO.
Bit 15: SCKE
0
1
Bit 14—Frame Synchronize Signal Output Enable (FSE): This bit is effective at master mode.
When 1 is set to this bit, SIOF initializes the frame counter, then starts operation.
Bit 14: FSE
0
1
Rev.6.00 Mar. 27, 2009 Page 616 of 1036
REJ09B0254-0600
Initial value:
Initial value:
R/W:
R/W:
Serial Control Register (SICTR)
Bit:
Bit:
SCKE
R/W
15
—
R
0
7
0
Description
Disable output of SCK_SIO (outputs 0)
Enable output of SCK_SIO
Description
Disable output of SIOFSYNC (outputs 0)
Enable output of SIOFSYNC
FSE
R/W
14
—
R
0
6
0
13
—
—
R
R
0
5
0
12
—
—
R
R
0
4
0
11
—
—
R
R
0
3
0
10
—
—
R
R
0
2
0
TXRST
TXE
R/W
W
9
0
1
0
(Initial value)
(Initial value)
RXRST
RXE
R/W
W
8
0
0
0
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