HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 162

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 3 Memory Management Unit (MMU)
4. The TLB exception address register (TEA) residing at address H'FFFFFFFC, which stores the
5. The MMU control register (MMUCR) residing at address H'FFFFFFE0, which makes the
The MMU registers are shown in figure 3.3.
Rev.6.00 Mar. 27, 2009 Page 104 of 1036
REJ09B0254-0600
logical address corresponding to a TLB or address error exception. This value remains valid
until the next exception or interrupt.
MMU settings described in figure 3.3. Any program that modifies MMUCR should reside in
the P1 or P2 area.
RC: A 2-bit random counter, automatically updated by hardware according to the
SV: Single virtual memory mode bit. Set to 1 for the single virtual memory mode,
AT: Address translation bit. Enables/disables the MMU.
TF: TLB flush bit. Write 1 to flush the TLB (clear all valid bits of the TLB to 0). Always
IX: Index mode bit. When 0, VPN bits 16 to 12 are used as the TLB index number.
0: Reserved bits. Always read as 0. Writing is ignored. However, 0 should also be
specified in a write to MMUCR only.
cleared to 0 for the multiple virtual memory mode.
following rules in the event of an MMU exception. When a TLB miss exception
occurs, all TLB entry ways corresponding to the virtual address at which the
exception occurred are checked, and if all ways are valid, 1 is added to RC; if
there is one or more invalid way, they are set by priority from way 0, in the order:
way 0, way 1, way 2, way 3. In the event of an MMU exception other than a TLB
miss exception, the way which caused the exception is set in RC.
reads 0.
When 1, the value obtained by EX-ORing ASID bits 4 to 0 in PTEH and VPN bits
16 to 12 are used as the TLB index number.
0: MMU disabled
1: MMU enabled
31
31
31
31
31
Figure 3.3 MMU Register Contents
Virtual address causing TLB-related
PPN
or address error exception
0
VPN
MMUCR
PTEH
PTEL
TTB
TTB
TEA
10
10
9
0
8
SV
8
V
0
7
0
7
00
7
PR SZ C D
6 5
6 4 3 2 1 0
RC
4
ASID
3 2 1
0 TF IX AT
SH 0
0
0
0
0