HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 528
HD6417727BP100BV
Manufacturer Part Number
HD6417727BP100BV
Description
IC SUPERH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP100BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 528 of 1098
- Download datasheet (7Mb)
Section 16 Realtime Clock (RTC)
Bit 3—Alarm Interrupt Enable Flag (AIE): Enables or disables interrupt generation when the
alarm flag (AF) is set to 1.
Bit 3: AIE
0
1
Bit 0—Alarm Flag (AF): The AF flag is set to 1 when the alarm time set in alarm registers (only
for the registers with ENB bit set to 1) match the clock and calendar time. This flag is cleared to 0
when 0 is written, but the previous value is retained when 1 is to be written.
Bit 0: AF
0
1
Note: * The value is not modified when 1 is written to AF.
16.2.16 RTC Control Register 2 (RCR2)
The RTC control register 2 (RCR2) is an 8-bit read/write register that controls periodic interrupts,
30-second adjustment ADJ, divider circuits RESET, and starting and stopping of the RTC count. It
is initialized to H'09 by a power-on reset. By a manual reset, bits except RTCEN and START are
initialized. RCR2 is not initialized and retains its contents in standby mode.
Rev.6.00 Mar. 27, 2009 Page 470 of 1036
REJ09B0254-0600
Initial value:
R/W:
Bit:
Description
An alarm interrupt is not generated when the AF flag is set to 1
An alarm interrupt is generated when the AF flag is set to 1
Description
Clock/calendar and alarm register have not matched since last reset to 0.
Clearing condition: When 0 is written to AF
Setting condition: Clock/calendar and alarm register have matched (only for the
registers with ENB set to 1)*
PEF
R/W
7
0
PES2
R/W
6
0
PES1
R/W
5
0
PES0
R/W
4
0
RTCEN
R/W
3
1
ADJ
R/W
2
0
RESET
R/W
0
1
(Initial value)
(Initial value)
START
R/W
0
1
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