HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 912
HD6417727BP100BV
Manufacturer Part Number
HD6417727BP100BV
Description
IC SUPERH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP100BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Section 27 I/O Ports
27.8
27.8.1
Note: * Undefined
Port L Data Register (PLDR) is an 8-bit read register that stores data for pins PTL7 to PTL2.
PL7DT to PL2DT bit corresponds to PTL7 to PTL2 pin. When the pin function is general input
port, if the port is read, the corresponding pin level is read. Table 27.7 shows the function of
PLDR.
PLDR is initialized to a power-on reset. It retains its previous value in software standby mode and
sleep mode, and by a manual reset.
Table 27.7 Read/Write Operation of the Port L Data Register (PLDR)
PLnMD1 PLnMD0 Pin State
0
1
Notes: *
Rev.6.00 Mar. 27, 2009 Page 854 of 1036
REJ09B0254-0600
Initial value:
1. Operation cannot be guaranteed when this bit it set to “reserved.”
Port L Data Register (PLDR)
Port L
0
1
*
Undefined
R/W:
Bit:
PL7DT
Other function H'00
Reserved *
Input
R
7
*
PL6DT
1
R
6
*
Read
⎯
Pin state
PL5DT
R
5
*
PL4DT
Write
Ignored (no affect on pin state)
⎯
Ignored (no affect on pin state)
R
4
*
PL3DT
R
3
*
PL2DT
R
2
*
—
R
1
*
(n = 2 to 7)
—
R
0
*
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