HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 349
![IC SUPERH MPU ROMLESS 240BGA](/photos/28/61/286131/240-lfbga__plbg0240ja-a_sml.jpg)
HD6417727BP100BV
Manufacturer Part Number
HD6417727BP100BV
Description
IC SUPERH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP100BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Memory Bus Width: The memory bus width in this LSI can be set for each area. In area 0, an
external pin can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on
reset as setting of MD4 and MD3 as below table .
Table 12.4 Correspondence between External Pins (MD4 and MD3) and Memory bus
MD4
0
1
For areas 2 to 6, byte, word, and longword may be chosen for the bus width using bus control
register 2 (BCR2) whenever ordinary memory, ROM, or burst ROM are used.
When the PCMCIA interface is used, set the bus width to byte or word. When synchronous
DRAM is connected to both area 2 and area 3, set the same bus width for areas 2 and 3. When
using the port function, set each of the bus widths to byte or word for all areas. For more
information, see section 12.2.2, Bus Control Register 2 (BCR2).
Area 3: H'0C000000
Area 0: H'00000000
Area 1: H'04000000
Area 2: H'08000000
Area 4: H'10000000
Area 5: H'14000000
Area 6: H'18000000
width in area0
MD3
0
1
0
1
Figure 12.3 Physical Space Allocation
burst ROM/PCMCIA
burst ROM/PCMCIA
synchronous DRAM
synchronous DRAM
Ordinary memory/
Ordinary memory/
Ordinary memory/
Ordinary memory/
Ordinary memory/
Ordinary memory
Memory Size
Reserved (Setting prohibited)
8 bits
16 bits
32 bits
Internal I/O
burst ROM
Rev.6.00 Mar. 27, 2009 Page 291 of 1036
Section 12 Bus State Controller (BSC)
The PCMCIA interface is shared
by the memory and I/O card
The PCMCIA interface is shared
by the memory and I/O card
REJ09B0254-0600
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