HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 352

• Manufacturer Part Number: HD6417727BP100BV
• Description: IC SUPERH MPU ROMLESS 240BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727BP100BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 Bus State Controller (BSC)
Bit 12—High-Z Control (HIZCNT): Specifies the state of the RAS and the CAS signals at
standby and bus right release.
Bit 12: HIZCNT
0
1
Bit 11—Endian Flag (ENDIAN): Samples the value of the external pin designating endian upon
a power-on reset. Endian for all physical spaces is decided by this bit, which is read-only.
Bit 11: ENDIAN
0
1
Bits 10 and 9—Area 0 Burst ROM Control (A0BST1, A0BST0): Specify whether to use burst
ROM in physical space area 0. When burst ROM is used, set the number of burst transfers.
Bit 10: A0BST1
0
1
Rev.6.00 Mar. 27, 2009 Page 294 of 1036
REJ09B0254-0600
Bit 9: A0BST0
0
1
0
1
Description
The RAS and the CAS signals are high-impedance state (High-Z) at standby
and bus right release.
The RAS and the CAS signals are driven at standby and bus right release.
Description
(On reset) Endian setting external pin (MD5) is low. Indicates this LSI is set
as big endian.
(On reset) Endian setting external pin (MD5) is high. Indicates this LSI is set
as little endian.
Description
Access area 0 as ordinary memory
Access area 0 as burst ROM (4 consecutive accesses).
Can be used when bus width is 8, 16, or 32.
Access area 0 as burst ROM (8 consecutive accesses).
Can be used when bus width is 8 or 16.
Access area 0 as burst ROM (16 consecutive
accesses). Can be used only when bus width is 8.
(Initial value)
(Initial value)