HD6417727BP100BV Renesas Electronics America, HD6417727BP100BV Datasheet - Page 380
![IC SUPERH MPU ROMLESS 240BGA](/photos/28/61/286131/240-lfbga__plbg0240ja-a_sml.jpg)
HD6417727BP100BV
Manufacturer Part Number
HD6417727BP100BV
Description
IC SUPERH MPU ROMLESS 240BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727BP100BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 380 of 1098
- Download datasheet (7Mb)
Section 12 Bus State Controller (BSC)
12.3.2
Area 0: Area 0 physical addresses A28 to A26 are 0'0. Addresses A31 to A29 are ignored and the
address range is H'00000000 + H'20000000 × n – H'03FFFFFF + H'20000000 × n (n = 0 to 6 and
n = 1 to 6 are the shadow spaces).
Ordinary memories such as SRAM, ROM, and burst ROM can be connected to this space. Byte,
word, or longword can be selected as the bus width using external pins MD3 and MD4. When the
area 0 space is accessed, a CS0 signal is asserted. An RD signal that can be used as OE and the
WE0 to WE3 signals for write control are also asserted. The number of bus cycles is selected
between 0 and 10 wait cycles using the A0W2 to A0W0 bits of WCR2. In addition, any number of
waits can be inserted in each bus cycle by means of the external wait pin (WAIT).
When the burst function is used, the bus cycle pitch of the burst cycle is determined within a range
of 2 to 10 according to the number of waits.
Area 1: Area 1 physical addresses A28 to A26 are 001. Addresses A31 to A29 are ignored and the
address range is H'04000000 + H'20000000 × n – H'07FFFFFF + H'20000000 × n (n = 0 to 6 and
n = 1 to 6 are the shadow spaces).
Area 1 is the area specifically for the internal peripheral modules. The external memories cannot
be connected.
Control registers of peripheral modules shown below are mapped to this area 1. Their addresses
are physical address, to which logical addresses can be mapped with the MMU enabled:
Those registers must be set not to be cached.
Area 2: Area 2 physical addresses A28 to A26 are 010. Addresses A31 to A29 are ignored and the
address range is H'08000000 + H'20000000 × n – H'0BFFFFFF + H'20000000 × n (n = 0 to 6 and
n = 1 to 6 are the shadow spaces).
Ordinary memories like SRAM and ROM, as well as synchronous DRAM, can be connected to
this space. Byte, word, or longword can be selected as the bus width using the A2SZ1 to A2SZ0
bits of BCR2 for ordinary memory.
When the area 2 space is accessed, a CS2 signal is asserted. When ordinary memories are
connected, an RD signal that can be used as OE and the WE0 to WE3 signals for write control are
also asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the
A2W1 to A2W0 bits of WCR2. In addition, any number of waits can be inserted in each bus cycle
by means of the external wait pin (WAIT) only when the ordinary memories are connected.
Rev.6.00 Mar. 27, 2009 Page 322 of 1036
REJ09B0254-0600
DMAC, PORT, SCIF, ADC, DAC, LCDC, PCC, SIOF, AFEIF, USBF, USBH, INTC
(except INTEVT, IPRA, IPRB)
Description of Areas
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