HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 82

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2. CPU
• Data Transfer Instructions
Rev.4.00 Mar. 27, 2008 Page 36 of 882
REJ09B0108-0400
Instruction
MOV
MOV.W @(disp,PC),Rn 1001nnnndddddddd
MOV.L @(disp,PC),Rn 1101nnnndddddddd
MOV
MOV.B Rm,@Rn
MOV.W Rm,@Rn
MOV.L Rm,@Rn
MOV.B @Rm,Rn
MOV.W @Rm,Rn
MOV.L @Rm,Rn
MOV.B Rm,@–Rn
MOV.W Rm,@–Rn
MOV.L Rm,@–Rn
MOV.B @Rm+,Rn
MOV.W @Rm+,Rn
MOV.L @Rm+,Rn
MOV.B R0,@(disp,Rn) 10000000nnnndddd
MOV.W R0,@(disp,Rn) 10000001nnnndddd
MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
MOV.B @(disp,Rm),R0 10000100mmmmdddd
MOV.W @(disp,Rm),R0 10000101mmmmdddd
MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
MOV.B Rm,@(R0,Rn)
MOV.W Rm,@(R0,Rn)
MOV.L Rm,@(R0,Rn)
#imm,Rn
Rm,Rn
Instruction Code
1110nnnniiiiiiii
0110nnnnmmmm0011
0010nnnnmmmm0000
0010nnnnmmmm0001
0010nnnnmmmm0010
0110nnnnmmmm0000
0110nnnnmmmm0001
0110nnnnmmmm0010
0010nnnnmmmm0100
0010nnnnmmmm0101
0010nnnnmmmm0110
0110nnnnmmmm0100
0110nnnnmmmm0101
0110nnnnmmmm0110
0000nnnnmmmm0100
0000nnnnmmmm0101
0000nnnnmmmm0110
Operation
#imm → Sign extension →
Rn
(disp × 2 + PC) → Sign
extension → Rn
(disp × 4 + PC) → Rn
Rm → Rn
Rm → (Rn)
Rm → (Rn)
Rm → (Rn)
(Rm) → Sign extension →
Rn
(Rm) → Sign extension →
Rn
(Rm) → Rn
Rn–1 → Rn, Rm → (Rn)
Rn–2 → Rn, Rm → (Rn)
Rn–4 → Rn, Rm → (Rn)
(Rm) → Sign extension →
Rn,Rm + 1 → Rm
(Rm) → Sign extension →
Rn,Rm + 2 → Rm
(Rm) → Rn,Rm + 4 → Rm 1
R0 → (disp + Rn)
R0 → (disp × 2 + Rn)
Rm → (disp × 4 + Rn)
(disp + Rm) → Sign
extension → R0
(disp × 2 + Rm) → Sign
extension → R0
(disp × 4 + Rm) → Rn
Rm → (R0 + Rn)
Rm → (R0 + Rn)
Rm → (R0 + Rn)
Execution
States
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
T
Bit
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