HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 75

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2.4.3
The instruction formats and the meaning of source and destination operand are described below.
The meaning of the operand depends on the instruction code. The symbols used are as follows:
• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement
Table 2.9
Instruction Formats
0 format
15
n format
15
m format
15
xxxx
xxxx
xxxx
mmmm
xxxx
nnnn
Instruction Format
Instruction Formats
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0
0
0
Source
Operand
—
—
Control register or
system register
Control register or
system register
mmmm: Direct
register
mmmm: Indirect
post-increment
register
mmmm: Indirect
register
mmmm: PC relative
using Rm
Rev.4.00 Mar. 27, 2008 Page 29 of 882
Destination
Operand
—
nnnn: Direct
register
nnnn: Direct
register
nnnn: Indirect pre-
decrement register
Control register or
system register
Control register or
system register
—
—
Example
NOP
MOVT
STS
STC.L SR,@-Rn
LDC
LDC.L @Rm+,SR
JMP
BRAF
REJ09B0108-0400
Rn
MACH,Rn
Rm,SR
@Rm
Rm
2. CPU