HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 251

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Conditions for Ending All Channels Simultaneously: Transfers on all channels end when the
NMIF (NMI flag) bit or AE (address error flag) bit is set to 1 in the DMAOR, or when the DME
bit in the DMAOR is cleared to 0.
• When the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or DMAC address
• When DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in the DMAOR aborts the
10.4.8
The space addressed by the DMAC is 3-cycle space. Therefore, when the CPU becomes the bus
master and accesses the DMAC, a minimum of three system clock (φ) cycles are required for one
bus cycle. Also, since the DMAC is located in word space, while a word-size access to the DMAC
is completed in one bus cycle, a longword-size access is automatically divided into two word
accesses, requiring two bus cycles (six basic clock cycles). These two bus cycles are executed
consecutively; a different bus cycle is never inserted between the two word accesses. This applies
to both write accesses and read accesses.
error occurs, the NMIF or AE bit is set to 1 in the DMAOR and all channels stop their
transfers. The DMAC obtains the bus mastership, and if these flags are set to 1 during
execution of a transfer, DMAC halts operation when the transfer processing currently being
executed ends, and transfers the bus mastership to the other bus master. Consequently, even if
the NMIF or AE bits are set to 1 during a transfer, the DMA source address register (SAR),
designation address register (DAR), and transfer count register (TCR) are all updated. The TE
bit is not set. To resume the transfers after NMI interrupt or address error processing, clear the
appropriate flag bit to 0. To avoid restarting a transfer on a particular channel, clear its DE bit
to 0.
Transfer is halted when the processing of a one unit transfer is complete. In a dual address
mode direct address transfer, even if an address error occurs or the NMI flag is set during read
processing, the transfer will not be halted until after completion of the following write
processing. In such a case, SAR, DAR, and TCR values are updated. In the same manner, the
transfer is not halted in dual address mode indirect address transfers until after the final write
processing has ended.
transfers on all channels. The TE bit is not set.
DMAC Access from CPU
10. Direct Memory Access Controller (DMAC)
Rev.4.00 Mar. 27, 2008 Page 205 of 882
REJ09B0108-0400