HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 725

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Notes: 1. Prewriting (setting erase block data to all 0s) is not necessary.
Increment address
2. Verify data is read in 32-bit (longword) units.
3. Make only a single-bit specification in the erase block register 1 (EBR1) and the erase block
4. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
register 2 (EBR2).
Figure 19.10 Erase/Erase-Verify Flowchart
No
No
Set block start address as verify address
H'FF dummy write to verify address
* 4
All erase block erased?
Set EBR1 and EBR2
Last address of block?
Verify data = all 1s?
Read verify data
Wait (t
End of erasing
SWE bit ← 1
Disable WDT
Enable WDT
ESU bit ← 1
ESU bit ← 0
SWE bit ← 0
Wait (t
Wait (t
Erase start
Wait (t
EV bit ← 1
Wait (t
Wait (t
E bit ← 1
Wait (t
E bit ← 0
EV bit ← 0
Wait (t
Wait (t
n ← 1
SSWE
CSWE
SESU
CESU
Yes
SEV
SEVR
SE
CE
CEV
) μs
Yes
)
Yes
)
)
)
)
)
)
)
* 1
No
* 3
* 2
Rev.4.00 Mar. 27, 2008 Page 679 of 882
19. Flash Memory (F-ZTAT Version)
SWE bit ← 0
Erase failure
EV bit ← 0
Wait (t
Wait (t
n ≤ 100?
CSWE
CEV
Yes
)
)
No
n ← n + 1
REJ09B0108-0400