HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 714

IC SUPERH MCU ROMLESS 112QFP

HD6417144F50V

Manufacturer Part Number
HD6417144F50V
Description
IC SUPERH MCU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet

Specifications of HD6417144F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
19. Flash Memory (F-ZTAT Version)
19.5.4
EBR2 specifies the flash memory erase block. EBR2 is initialized to H'00 when a high level is
input to the FWP pin. It is also initialized to H'00, when the SWE bit in FLMCR1 is 0 regardless
of value in the FWP pin. Do not set more than one bit at a time in EBR1 and EBR2, as this will
cause all the bits in EBR1 and EBR2 to be automatically cleared to 0.
19.5.5
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER settings should be made in user mode or user
program mode. To ensure correct operation of the emulation function, the ROM for which RAM
emulation is performed should not be accessed immediately after this register has been modified.
Normal execution of an access immediately after register modification is not guaranteed.
Rev.4.00 Mar. 27, 2008 Page 668 of 882
REJ09B0108-0400
Bit
7 to 4
3
2
1
0
Bit
15 to 4 —
3
Bit Name Initial Value
EB11
EB10
EB9
EB8
Bit Name Initial Value
RAMS
Erase Block Register 2 (EBR2)
RAM Emulation Register (RAMER)
All 0
All 0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
When this bit is set to 1, 64 kbytes of EB11
(H'030000 to H'03FFFF) are to be erased.
When this bit is set to 1, 64 kbytes of EB10
(H'020000 to H'02FFFF) are to be erased.
When this bit is set to 1, 64 kbytes of EB9 (H'010000
to H'01FFFF) will be erased.
When this bit is set to 1, 32 kbytes of EB8 (H'008000
to H'00FFFF) will be erased.
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
RAM Select
Specifies selection or non-selection of flash memory
emulation in RAM. When RAMS = 1, the flash
memory is overlapped with part of RAM, and all flash
memory blocks are program/erase-protected. When
RAMS = 0, the RAM emulation function is disabled.

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